Timeline for Op amp integrator output has DC offset even when a coupling capacitor is used
Current License: CC BY-SA 3.0
12 events
| when toggle format | what | by | license | comment | |
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| Mar 11, 2018 at 16:57 | vote | accept | Qubit1028 | ||
| Mar 11, 2018 at 6:42 | comment | added | a concerned citizen | @Qubit1028 I thought that when you used the voltage probe in LTspice you were essentially adding a high resistance load to ground No, the probes do not act like their real world counterparts. Every "interaction" between the probe(s) and the elements of a schematic is done virtually, as if with the hand of God. | |
| Mar 11, 2018 at 5:35 | comment | added | Sredni Vashtar | ... (aw, I hoped one comment would have been enough). Where was I? ...to significantly charge/discharge the cap in order to remove the offset. When you need many many cycles to alter the voltage of your cap, if you look at the fist ten, or hundred periods, the output wave appears to conserve its offset unaltered. | |
| Mar 11, 2018 at 5:32 | comment | added | Sredni Vashtar | It appears the blocking caps are too big and it takes an enormous amount of time (relatively speaking) to remove the average value from the output (and input, should it be offset too) signal. You can see this effect simulating a simple CR circuit with a pulsed and offseted input: you will see that when tau=RC is much bigger than the period of the input signal, the output appears to be still affected by the offset. The basic reason is that caps cannot instantaneously change voltage, so the edges of the square wave will pass unharmed, while the time between edges is not enough to significantly.. | |
| Mar 11, 2018 at 2:30 | answer | added | Big6 | timeline score: 3 | |
| Mar 11, 2018 at 1:22 | history | edited | Qubit1028 | CC BY-SA 3.0 | added 183 characters in body |
| Mar 11, 2018 at 1:20 | comment | added | Qubit1028 | Ah, yes, running the simulation for a longer time did indeed result in zero offset in the output. I'm going to edit my question to show the new result. But, my question now is what time constant causes this behavior? | |
| Mar 11, 2018 at 1:04 | comment | added | analogsystemsrf | The peaks of the triangle waves are dropping, as you look from left to right. However, given the DC blocking on vin(-), the opamp still needs ZERO VOLTS between Vin- and Vin+, or you'll have rail-to-rail Vout. And the bias on Vin+ is +4.5 volts. | |
| Mar 11, 2018 at 0:23 | comment | added | Big6 | Uhm, run the simulation for longer, say, 1 minute, you're running it for only 1ms. I think it may be a transient state. | |
| Mar 11, 2018 at 0:18 | comment | added | Qubit1028 | I tried that but the result was the same. Anyways, I thought that when you used the voltage probe in LTspice you were essentially adding a high resistance load to ground, correct? It's not clear to me how the bias on the non-inverting input could be the issue because when I remove the feedback capacitor and feed in a sine wave signal, I get the expected AC output with no DC offset. | |
| Mar 11, 2018 at 0:13 | comment | added | Big6 | no load at the output, no path to dc ground, then floating dc wise. Add a load, even if it is 1GOhm, and see what happens. | |
| Mar 11, 2018 at 0:08 | history | asked | Qubit1028 | CC BY-SA 3.0 |