Vout is represented as a battery because it's such a relatively large capacitance that you can't effect its voltage. It could just as well be a very large capacitor at the time scales they are considering but for simplicity, they want you to ignore any possible charge-discharge characteristics of capacitors on the output. While the device is in the off state, all current from Idc is charging the battery but since it's such a high capacity, the voltage doesn't change so Vds is the battery voltage plus the Vf of the diode. As the gate reaches Vth the current in the device starts to increase and the current charging the battery decreases proportionally which means that Vds remains the same. Once the current of Idc is fully flowing through the device, the Vds drops below Vout+Vf and the diode turns off. It think it would be very useful if Rds and Rbat+Rdiode were included in that graph. It would make some things easier to visualize.
In stage 3, the drain current stays the same because of the inductive current source. Remember that the collapse of the magnetic field has the effect of trying to keep the current steady (at short time scales). Cgd is relatively small, so the charging current can be neglected in light of the much larger Ids. Vds is falling at his point because Rds is falling but the Ids remains constant.
Edit: During stage 3, the Miller plateau (on Vgs) is caused by the change in Vds being coupled through the Cgd which keeps the voltage on the gate from increasing at the same rate as it did in stage 1 & 2 even though it continues to charge. In stage 4, the Vgs continues to rise after Vds approaches it's minimum. Vgs in stage 4 typically looks more like a capacitor charging than a linear slope but for illustration purposes, I think it's okay.
There is a nice explanation of Miller plateau here
