Timeline for STM32L4 slow toggling GPIO pins
Current License: CC BY-SA 4.0
6 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Aug 17, 2021 at 14:51 | comment | added | D. K. | Thank you! So I may play a little bit trying to push from 6MHz to closer to 10MHz. Or just use the max possible speed of 120MHz... At the end, nothing strange about the code, maybe just overhead. | |
| Aug 17, 2021 at 14:48 | vote | accept | D. K. | ||
| Aug 17, 2021 at 13:44 | comment | added | Jeroen3 | @D.K. 50 Mhz is the maximum speed the IO can work in due to the APB. You can only change the output bit every 1/100 Mhz, so half that is the maximum toggle. The 4 bus ops is, read-const, write-register, read-const, write-register for two edges. That is also limited to the 100 MHz APB clock. The 10 instructions is just how much it takes on average, loop, read const, load address, write register, branch loop. | |
| Aug 17, 2021 at 13:20 | comment | added | D. K. | Actually, you made me think... When you say 50MHz with timer you mean something like PWM signal, right? Not register access or something. | |
| Aug 17, 2021 at 12:37 | comment | added | D. K. | Thank you for the clarifications! So, bare assembler from ram would always take 10 instructions? Is it related to the number of pins I toggle? From there I scale by the clock for ideally max speed possible? Is the same 4 bus ops defined too? I guess that may be the limitation that stops me... with overhead 6MHz+ sounds reasonable. Is this typical calculation for this MCU or like general rule? | |
| Aug 16, 2021 at 13:42 | history | answered | Jeroen3 | CC BY-SA 4.0 |