Timeline for Execute module one after another using flag status
Current License: CC BY-SA 3.0
8 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Mar 13, 2013 at 19:40 | answer | added | pre_randomize | timeline score: 2 | |
| Mar 13, 2013 at 12:03 | answer | added | Martin Thompson | timeline score: 2 | |
| Mar 13, 2013 at 11:08 | comment | added | pjc50 | In Verilog, everything in 'always' blocks executes all the time, as triggered by its '@' conditions. So multiply_4 gives you multiplied result whenever its input changes. Note that it's probably not synthesizable. | |
| Mar 13, 2013 at 10:52 | history | edited | Shreyas Patel | CC BY-SA 3.0 | added 22 characters in body |
| S Mar 13, 2013 at 8:41 | history | edited | clabacchio | CC BY-SA 3.0 | Grammar, Aligned Code |
| S Mar 13, 2013 at 8:41 | history | suggested | pre_randomize | CC BY-SA 3.0 | Grammar, Aligned Code |
| Mar 13, 2013 at 8:27 | review | Suggested edits | |||
| Mar 13, 2013 at 8:41 | |||||
| Mar 13, 2013 at 4:22 | history | asked | Shreyas Patel | CC BY-SA 3.0 |