Timeline for Clock domain crossing without synchronisers
Current License: CC BY-SA 4.0
14 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Dec 16, 2022 at 16:11 | vote | accept | Elzaidir | ||
| Dec 16, 2022 at 16:11 | answer | added | Elzaidir | timeline score: 0 | |
| Nov 26, 2022 at 2:48 | comment | added | Dave Tweed | If the SPI clock is intermittent, it may be necessary to insert one or more "dummy" bytes into the protocol on the SPI master side in order to create the additional clock edges you need. Or if the master is polling for command completion anyway, that might serve the purpose just as well. | |
| Nov 24, 2022 at 14:30 | comment | added | Elzaidir | @DaveTweed The SPI clock comes directly from the SCK pin, so we don't have an active clock before sending data. A pulse synchroniser introduces at the very least one clock delay but the data are needed immediately. "* there's no metastability generated there*" Yes you're right, I should have said "The signals have had the time to stabilise. | |
| Nov 24, 2022 at 14:27 | comment | added | Elzaidir | @MituRaj The SPI interface is actually "stalled" by returning a busy packet until the command has been processed. We can't increase the core frequency just for the SPI, as the ASIC is supposed to be as low power as possible. | |
| Nov 24, 2022 at 14:23 | comment | added | Elzaidir | @user_1818839 The main domain is very slow because the ASIC is a very low power sensor. Correctly sampling with a higher clock would mean at least a 20x increase in frequency, and thus in consumption. | |
| Nov 20, 2022 at 2:23 | comment | added | Dave Tweed | One other point. You said: "Because the pulse synchroniser introduces a delay, we know metastabilities have been resolved once the data is being used by the controller." But there are no metastabilities on this data, since it is clocked only in the source domain. And it is guaranteed not to be changing at the time it is sampled in the destination domain, so there's no metastability generated there, either. | |
| Nov 19, 2022 at 2:20 | comment | added | Dave Tweed | Your description for the command (SPI to controller) sounds fine. But I'm not following why the other direction is any "trickier" -- it can use the exact same principle. The key concept is that the SPI slave can't change the command value between when it sends the command request and when it gets the command acknowledge back. Similarly, the controller cannot change its response value between when it sends the acknowledge and when it gets the next command request. In other words, the protocol can be completely symmetical, despite the large difference in clock speeds. | |
| Nov 18, 2022 at 20:01 | comment | added | Mitu Raj | SPI domain is 10 times slower than main domain. That's weird. Don't you have data losses then all the time? Because serial data is continuous on SDI reception for example and cannot be 'stalled', and you don't have buffers. One thumb rule I follow is the core logic works 4x times faster than its SPI interface. | |
| Nov 18, 2022 at 17:06 | comment | added | Neil_UK | Although the domains are different speeds, are they synchronous? Is the 1M domain clocked from the 10M domain? If so, you can use this to avoid metastability. You really need to draw us a timing diagram. If you were asking a circuit question, we would need a schematic. For this sort of question, we need the timing diagram. And maybe, in drawing it, you might find the answer to your question. Metastability has attracted a lot of attempts at neat solutions, and none work. The only solutions have a complexity and wait time requirement equivalent or greater than doing it properly. | |
| Nov 18, 2022 at 17:02 | comment | added | user16324 | frame challenge : why is the main domain so slow? | |
| Nov 18, 2022 at 16:34 | history | edited | Elzaidir | CC BY-SA 4.0 | Invert S and R in the diagram |
| S Nov 18, 2022 at 16:32 | review | First questions | |||
| Nov 18, 2022 at 16:34 | |||||
| S Nov 18, 2022 at 16:32 | history | asked | Elzaidir | CC BY-SA 4.0 |