Timeline for Do extra PCIe lanes improve latency?
Current License: CC BY-SA 4.0
4 events
| when toggle format | what | by | license | comment | |
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| Nov 2, 2023 at 21:38 | vote | accept | Maestro | ||
| Nov 2, 2023 at 21:25 | comment | added | Marcus Müller | at a large amount of data like 1MB that we assume to not be limited by CPU interrupt latency, e.g. because it's done purely through DMA, roughly one fourth of the time, to a reasonably good approximation. Looks different when you ask for a single 4KB block. | |
| Nov 2, 2023 at 21:24 | comment | added | Maestro | Is it possible to make any estimate about how much slower it will perform with 1 lane vs 4 lanes (provided you operate below 1 GB/s) to read 1 MB of data for example? If I understand correctly, most of the time is lost by waiting for the transfer to start, and not the actual transfer itself. So it will not be 4 times slower. So what would be a (very rough) estimate of the reduction? | |
| Nov 2, 2023 at 20:56 | history | answered | Marcus Müller | CC BY-SA 4.0 |