Timeline for Why does this high pass filter/rc differentiator behave like this?
Current License: CC BY-SA 4.0
6 events
| when toggle format | what | by | license | comment | |
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| Aug 26, 2024 at 4:39 | comment | added | BK303 | @Mahad when the clk is steady high and circuit output is zero, the left side of the cap is positive with respect to right side and no current is flowing in R or C. When the input clk switches to low (0 V) then the voltage across the cap CAN NOT change until the charge flows, which must take time because limited by R and not instant. As the left side of the cap is forced to new voltage with respect to gnd by Vclk driver switching to gnd, yet the left side of the cap to MUST remain higher voltage than the right side, so the right side becomes negative with respect to ground. | |
| Aug 25, 2024 at 1:32 | vote | accept | Mahad | ||
| Aug 25, 2024 at 1:20 | comment | added | nanofarad | @Mahad The cap discharges, causing a current to flow in the opposite direction, which (by Ohm's law) gives you the negative spike. I'm not sure why D.A.S. mentioned CMOS here since there doesn't seem to be any MOS gates involved in the circuit. | |
| Aug 25, 2024 at 0:45 | comment | added | Tony Stewart EE since 1975 | No the resistor drains the cap to gnd. So a negative edge tries to go to -(Vdd) which exceeds "Not to exceed" levels for CMOS then returns to gnd. | |
| Aug 25, 2024 at 0:22 | comment | added | Mahad | Hi. Thanks for your response, appreciate it. However, I have one more question. When CLK goes low, cap should discharge right? dv will be negative therefore current is negative/opposite direction and CLK sinks the current? But how can the vout be negative? Vout = Vr since they are parallel but Vout being negative implies that GND is higher potential than the other side of the resistor and charge flows from GND? How can that be the case? Thanks. | |
| Aug 24, 2024 at 23:57 | history | answered | nanofarad | CC BY-SA 4.0 |