Timeline for How are multiple DDR5 DIMMs wired into to the same channel?
Current License: CC BY-SA 4.0
12 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Dec 19, 2024 at 21:30 | comment | added | KJ7LNW | @Hearth, its an AMD 9950X which supports 128GB, and these are 4x 32GB modules with sequential serial numbers. | |
| Dec 19, 2024 at 3:52 | comment | added | Hearth | What processor are you using? Sometimes they just can't use more than a certain amount of RAM, so if you're trying to cram huge amounts of RAM into the computer it may be that. The motherboard specifies that it supports no more than 256 GB of RAM, so if you have more than that for some reason (that'd be an absurd amount of RAM though), I'd expect issues. | |
| Dec 19, 2024 at 0:10 | comment | added | KJ7LNW | @Attie, well an identical system has the same problem, so now I'm suspecting a compatibility issue. That also confirms that a reseat is unnecessary. Thanks for the DDR5 feedback, you saved me some time for sure. | |
| Dec 18, 2024 at 23:32 | comment | added | Attie | It's odd that only one is working for each channel - are you confident that the other just doesn't work, and is it the same socket for both channels? ... is this potentially a limitation of your CPU? (I would be quite surprised if you had connectivity issues for one socket on each channel, but nothing else) | |
| Dec 18, 2024 at 22:25 | comment | added | KJ7LNW | @Attie, only one socket on each memory channel is working. Trying to understand wiring topology to know if a re-seat is warranted since both channels do work with a single socket populated for each channel. | |
| Dec 18, 2024 at 22:19 | comment | added | Attie | A single DDR5 UDIMM has 2x 32-bit sub-channels, each sub-channel has 2x Chip-Select signals, each UDIMM socket therefore gets a separate set of CS signals. Your mainboard has 4x UDIMM sockets, two for each memory channel. If you've confirmed that all of your modules work, and have confirmed that both of the sockets on each memory channel are operational, then why is the wiring in question? | |
| Dec 18, 2024 at 22:08 | comment | added | KJ7LNW | @Attie yes it is consumer equipment, but the question is about DDR5 wiring | |
| Dec 18, 2024 at 22:07 | comment | added | Attie | It is of course possible to reseat both CPU and DIMMs and get improved signal integrity (either by chance/luck or with cleaning), and this may even get memory to train that previously failed... but unless the cleaning was visibly required, I doubt the result would be stable. If you were designing a mainboard, then I think this question would fit (with a refocus on SI and validation), but as you're discussing consumer equipment, I think it's off-topic. Sorry. | |
| Dec 18, 2024 at 22:07 | comment | added | KJ7LNW | @Attie wow, ok, so maybe I just try the reseat. I was expecting that the dimms on the same channel were on a bus with chipselect pins or low-bit-address-permutation or something, but that the IO lines were basically the same for the same channel. | |
| Dec 18, 2024 at 22:05 | comment | added | Attie | Bus loading is also dependent on things like the module's rank and whether your modules are buffered/registered, etc... the modules you've linked are not buffered/registered, the rank is unspecified, and there's no detailled datasheet (yay). | |
| Dec 18, 2024 at 21:43 | comment | added | Voltage Spike♦ | This is highly processor dependent, we need a block diagram of the system or schematic | |
| Dec 18, 2024 at 21:39 | history | asked | KJ7LNW | CC BY-SA 4.0 |