Timeline for DRAM - Address choosing
Current License: CC BY-SA 4.0
7 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Jul 7 at 17:17 | comment | added | Ben Shaines | Oh right, thanks!!! | |
| Jul 7 at 17:04 | comment | added | Dave Tweed | This part of the memory architecture is the same for both reading and writing. The difference between reading and writing occurs on the bit lines. | |
| Jul 7 at 15:53 | vote | accept | Ben Shaines | ||
| Jul 7 at 15:53 | comment | added | Ben Shaines | Great, thank you very much!!! Mind if I ask something else? how will it be different if I was reading? Sorry for this not related question, I want to understand the difference. | |
| Jul 7 at 15:47 | comment | added | Dave Tweed | Yes, all address lines must be valid (not changing) before the precharge pulse starts. A proper design will have some timing margin here to allow for manufacturing variations. | |
| Jul 7 at 15:34 | comment | added | Ben Shaines | Hi, thanks for the help. So in our case, regarding the valid, during the precharge, the valid has stable "1"? Also, in the graphs I gave, we see the valid bit is a little before the precharge, is it in purpose or just bad drawing? it should start before the precharge? | |
| Jul 7 at 15:25 | history | answered | Dave Tweed | CC BY-SA 4.0 |