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I have been learning about CMOS Tri State inverters, and I was wondering which one of these two ways is a better implementation of this circuit.

The first is what we see in all textbooks :

  1. With the middle two transistors connected to Enable (EN) and Enable bar (~EN)

    schematic 1

Or the second -

  1. Or with the Enable and Enable bar connected to the transistors closest to the power and gnd nodes and the input signal connected to the gates of the middle two transistors:

    schematic 2

    Vcc is power and VSS is ground

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  • \$\begingroup\$ Note that when you use the CircuitLab button on the editor toolbar and "Save and Insert" on the editor an editable schematic is saved in your post. That makes it easy for us to copy and edit in our answers. You don't need a CircuitLab account, no screengrabs, no image uploads, no background grid. \$\endgroup\$ Commented Apr 2, 2020 at 21:00
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    \$\begingroup\$ Assuming this is a homework question, can you think of one more characteristics that would make one configuration quantitatively better than the other? \$\endgroup\$ Commented Apr 2, 2020 at 21:06
  • \$\begingroup\$ Not home work in the strict sense, but here is what I think, the second configuration has the advantage that the input signal (In) will have to drive a smaller load capacitance, however in the first circuit the switch can already be 'turned on' by the enable signal, and the inout signal will not have to 'wait' to be inverted. \$\endgroup\$ Commented Apr 2, 2020 at 21:11
  • \$\begingroup\$ @Atul, which component do you mean when you say "the switch"? \$\endgroup\$ Commented Apr 2, 2020 at 21:36
  • \$\begingroup\$ @ThePhoton - By switch I mean the two transistors connected to EN and ~EN. \$\endgroup\$ Commented Apr 2, 2020 at 21:44

3 Answers 3

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I don't think it matters, the order of the transistors is arbitrary since they're wired in series. You can find examples of both.

This series of lecture notes shows an example that is the same as (1): http://www-inst.eecs.berkeley.edu/~cs150/sp10/Lecture/lec08-cmos.pdf

That said, they prefer a transmission-gate approach which looks like this:

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ I think it would matter. You'd be loading the two signal paths differently \$\endgroup\$ Commented Apr 2, 2020 at 23:42
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The second scheme is bad because when it is opaque, the changing input will introduce noise resulted from charge-sharing.

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The answer above that charge-sharing is the reason to prefer the first version is absolutely correct.

The tri-state inverter is useful as a CMOS latch. You put two together and you have a basic design for a DFF (D-type flip-flop). In such a design, the loading on the master output is very small, and the charge sharing event that occurs when the input switches (in design #2) may cause a bump that affects timing and may even give signal integrity problems (especially if you are doing a design without a keeper, which you might do for some reason---but it doesn't really help that much to add a keeper to the output either).

Dynamic domino circuits more generally (the circuit family of which this is NEARLY the simplest example) have big problems with charge sharing. This is why they are not used very much these days. They used to be used heavily in high-performance designs.

One moral of this story: if you are stringing together MOSFETs into something that's not a static CMOS gate where the pull-up and pull-down are duals, there are actually a lot subtle analog effects that can intrude and make a mess of things.

BTW I used to have this exact question in one of my early homework assignments when I taught this stuff. Then ask, why do you prefer #2? Well you prefer #2 because it's an easier layout, fewer crossovers, so you can just run the clocks in polysilicon. Of course no one does that anymore.

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