I can't add an offset voltage 2.5 V to my analog signal. The circuit is attached.
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- \$\begingroup\$ Add an large capacitor C > 0.16/(F_min * R3||R4) in series with V1. \$\endgroup\$G36– G362021-04-17 11:27:49 +00:00Commented Apr 17, 2021 at 11:27
- \$\begingroup\$ You need an impedance from your source as well, otherwise it wins over your voltage divider at all times. \$\endgroup\$winny– winny2021-04-17 11:42:34 +00:00Commented Apr 17, 2021 at 11:42
- \$\begingroup\$ thank you very much it works , i add 100 nF capacitor in series but i don'understand why i must add a capacitor in series and where i can find your formule ? \$\endgroup\$Selim Ulusoy– Selim Ulusoy2021-04-17 11:49:48 +00:00Commented Apr 17, 2021 at 11:49
- \$\begingroup\$ electronics.stackexchange.com/questions/301921/… \$\endgroup\$G36– G362021-04-17 11:52:00 +00:00Commented Apr 17, 2021 at 11:52
- \$\begingroup\$ its not that you need to add a capacitor, it's that you need to add impedance and the capacitor will add that for a given frequency. \$\endgroup\$user16222– user162222021-04-17 13:00:50 +00:00Commented Apr 17, 2021 at 13:00
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2 Answers
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The problem is that you have connected your voltage sources in parallel. The source impedance of your voltage divider is 50 kΩ, while the impedance of your AC source is zero. When you connect these in parallel, the AC source shorts out the DC source, and you get zero offset.
If you want to add voltages, you need to connect them in series. Connect V1 between the junction of the two resistors and the scope.
However, in many applications, both sources need to be referenced to the same node (usually called "ground"). In that case, you can build a circuit that takes the "average" of the two voltages, which includes the operation of adding them together. To do this, they need to have the same source impedance. Take your original circuit and add a 50 kΩ resistor in series with V1. But in this case, both voltages also get divided by two, giving you a 0.5 V AC signal with a 1.25 V DC bias.
Or you can use an impedance that varies with frequency as G36 suggested in a comment, such as a capacitor. This creates a high-pass filter for the AC signal, and a low-pass filter for the DC bias. With the correct selection of component values, neither signal is significantly attenuated.
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1 Add a 1.0 uF ceramic capacitor between the V1 + terminal and the R3-R4 node.
- \$\begingroup\$ It is basically the correct advice, but the ceramics are the ones with the worst linearity of them all due to huge cap change with DC bias. An electrolytic or film cap will be better \$\endgroup\$tobalt– tobalt2021-04-17 12:55:20 +00:00Commented Apr 17, 2021 at 12:55