The cycle defining reliably getting data from Qa to Db will have three basic components:
- Clock-to-Q (Tcq) of Qa (not sure why they didn't mention this)
- Prop delay (Tpd, time-of-flight) from Qa to Db
- Db setup time (Tsu)
This assumes CA and CB have no skew.
Let’s define Tskew as T(CA) - T(CB). We then have a cycle time of:
- Tcyc = Tcq + Tpd + Tsu + Tskew
What does this mean? A positive value for Tskew slows down your cycle, while a negative one speeds it up.
If CB is later than CA, you can deduct this inserted delay from the achievable cycle time. That is, Tskew = T(CA) - T(CB) is a negative value. This is sometimes called helpful skew (but mind the hold time).
Think of it this way: by moving the receiving flop’s clock later, you’re also moving its sample window later. This gives more setup time. You get this when Tskew is negative.
In the other hand, if CB is earlier than CA, then you add this delay to the achievable cycle time (but it helps hold time). That is, Tskew is positive.
Let's work some examples. Say you have these parameters for your flops:
- Tcq = 3ns
- Tpd = 1ns
- Tsu = 2ns
Without considering clock skew, adding them together we get a best-case cycle time of 6ns.
Now, let's add 1ns delay to CB relative to CA:
- Tskew = T(CA) - T(CB) = (0ns) - (1ns) = -1ns
- Tcyc = (Tcq + Tpd + Tsu) + Tskew = (3+1+2) + (-1) = 4ns.
Delaying the receiving flop achieves a shorter cycle time. Again, this is helpful skew.
However, if we instead delay CA with respect to CB, Tskew is a positive value:
- Tskew = T(CA) - T(CB) = (+1ns) - (0ns) = +1ns
- Tcyc = (Tcq + Tpd + Tsu) + Tskew = (3+1+2) + 1 = 7ns.
This is unhelpful skew as far as cycle time, but it improves hold time.
Many board-level systems with ICs sharing a clock are made this way: they will feed the clock to the receiver first, then the transmitter, in order to ensure hold time. It's a compromise to ensure system reliability without having to think too hard.
More advanced designs (boards and chips) will seek to minimize clock skew by using clock trees that seek to balance the clock distribution delay between flip-flops, ensuring best possible cycle time without compromising hold time.
In the bigger picture, when designing a clocked system you need to consider variations in all the paths to establish reliable timing, both setup and hold. Clock skew uncertainty will influence both.
More here: https://www.allaboutcircuits.com/technical-articles/what-is-clock-skew-understanding-clock-skew-and-clock-distribution-networks/
