As I gather from your question, you are in the course of studying the high-speed transceiver architecture and design implementation. You seem to know that the slicer is a limiter used in the decision-feedback equalizer (DFE) circuitry. If not, you can learn it from Razavi's article The Decision-Feedback Equalizer and recognize that DFE is invented to fight intersymbol interference (ISI) errors. When reading the article, pay attention how Razavi intoduces a clocked comparator component into the control-feedback loop, connecting the delay stage and the slicer into one component, a flipflop FF [page 14 (2/5), Figure 4(c)]. For convenience of readers of this post, I'm citing Razavi's explanation:
This issue [the amplitude noise amplification in the feedback loop] can be remedied if the delay element is followed by a limiter, also known as a “slicer,” so as to remove the amplitude noise [Figure 4(b)]. The loop thus stops the noise from circulating and acts as a nonlinear equalizer. For robust operation, we replace the delay stage and the slicer with a flipflop (FF) [Figure 4(c)], recognizing that typical FFs provide both a one-period delay and limiting action on the amplitude. We can say the loop feeds the FF’s decision back to the input, hence the term DFE.
The design with flipflops is prone to metastability and other well-known complications, as well. The article proceeds with considering DFE speed limitations (flipflop timing parameters, propagation delay, which, of course, are not metastability issues) and how other nonidealities can be alleviated.
Summing up, in DFE (part of the high-speed transceiver), the slicer component is a component of clocked comparator and its metastability issues should be considered in this context. To help you proceed with your sutudy, I recommend you the article Simulation and Analysis of Random Decision Errors in Clocked Comparators, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 56, NO. 8, AUGUST 2009. There is a copy of this article on the Texas A&M University site, https://people.engr.tamu.edu/spalermo/ecen689/simulation_analysis_clocked_comparators_kim_tcas1_2009.pdf. The authors elaborate the linear time-varying model of clock comparators which considers slicer metastability issues and give the BER formulas for 90- and 65-nm CMOS process designs. To support my claim that the article tackles the metastability issues, I'm citing two exerpts from the article:
While the signals in clocked comparator circuits generally make large-signal excursions during the operation, many of the important characteristics can be analyzed based on the small-signal response of the comparator when it is near the metastable point (i.e., when the input signal is conditioned so that the comparator cannot reach a firm decision within the cycle). It is because the metastable point is where the comparator decision output is most sensitive to noise and the comparator is most likely to generate decision errors.
and
However, in practical simulation, we found that the noise observed at the comparator output is not strictly additive, especially when the comparator is operating very close to the metastable point. It is possible that noises modulated by deterministic, large-signal effects such as kick-back noise overwhelm the additive Gaussian noise that we are trying to measure. As described later in Section IV, we found that it yields more accurate results to estimate the Gaussian noise power from a set of decision error probability measurements with nonzero input signal values’s for which the comparator is slightly apart from the metastable point and the additive Gaussian noise has the dominant effect on the error probability.
