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I have been given the following circuit:

digital circuit

I am given the respective propagation delays and asked to find the minimum clock period for proper functioning of the circuit without any glitches:

question

I calculated the delays and noted them down (my solution):

my solution

Based on this I entered 17 as Flip Flop A seemed to have the largest delay. However this is the incorrect answer.

I have ignored the NOT gate output delay as it is guaranteed to be ready by the time Tcq is ready (Tcq > Tnot). I have also assumed that the input x may be changed only at the same time as positive clock edge is triggered.

Where am I incorrect? How to approach it correctly?

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  • \$\begingroup\$ Welcome to SE/EE! Please take the tour to learn how this site works, and read "How to Ask" and other pages of the help center. Then come back and edit your question to add an actual question. Currently I see just statements. \$\endgroup\$ Commented Dec 22, 2024 at 9:45
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    \$\begingroup\$ @devnull Since this task is about calculation of clock periods, the circuit does not need to have a real use or to work at all. However, a quick simulation suggests that it lets the FSM advance at every second clock. \$\endgroup\$ Commented Dec 22, 2024 at 13:45
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    \$\begingroup\$ Please clarify, as asked by @devnull. It is important to know how exactly x changes in relation to the clock. This is probably relevant. -- Otherwise, at a first glance your calculations looks correct, if I assume that x receives a signal constantly over multiple clock periods. \$\endgroup\$ Commented Dec 22, 2024 at 13:55
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    \$\begingroup\$ @devnull Yes. Sorry for the wording, English is not my native language. \$\endgroup\$ Commented Dec 22, 2024 at 13:57
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    \$\begingroup\$ Perhaps this is the source of the difference. You might need to ask the authors of the task. \$\endgroup\$ Commented Dec 22, 2024 at 16:10

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but to keep things simple x changes exactly on positive clock edge

The question does seem to be missing relevant information. Input x should not be asynchronous, otherwise it would not be possible to guarantee correct timing (setup and hold). Since it needs to be synchronized, it is the output of another flip-flop, not simultaneous with the clock itself. If that is the case and this other flip-flop has the same propagation delay, 18 is indeed the critical path. The 6 would come from the other flip-flop, not the one in the diagram. The loop-back path with 17 ns delay would not be the critical one, if this synchronization is to be assumed.

I agree with the comment that recommends further clarification from the authors.

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  • \$\begingroup\$ thank you very much. does this mean that if 1) x is a constant which never changes, Or 2) if it is strictly not coming from another flipflop, and it changes exactly at the same time as positive edge of clock, then the minimum period will be 17? \$\endgroup\$ Commented Dec 23, 2024 at 3:46
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    \$\begingroup\$ @mayabed Probably x is the output of another flip-flop clocked by the same clock, as described. It says something that the expected answer is "18" and not "17, but 18 if ..." However, only you can verify this by asking your teachers. That's why we asked for clarification. \$\endgroup\$ Commented Dec 23, 2024 at 10:01
  • \$\begingroup\$ thank you. i will ask them and get back... However, can you tell me if i was correct on the above scenarios in my previous comment? \$\endgroup\$ Commented Dec 24, 2024 at 5:15

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