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Regarding a NOR DRAM enter image description here

We had a question regarding address choosing at a test enter image description here The professor said that the correct graph is the second, reason:
The correct option is the second one, because after the precharge phase is completed, it is no longer possible to change the address. If the address lines are modified during stabilization, the selected word line (WL) will not be properly activated.

Can anybody explain it to me please? I don't understand why isn't the first graph is actually true, me and other students also thought the same...
Also, what really is the term "valid" here means? No idea about it..

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    \$\begingroup\$ Multiple FETs are on columns and rows. You must select a column of 4, before you can access a specific row of 2. \$\endgroup\$ Commented Jul 7 at 17:15
  • \$\begingroup\$ @StainlessSteelRat To be honest, didn't understand what it means specific row of 2. or column of 4. But I got help, thanks though :) \$\endgroup\$ Commented Jul 7 at 17:18
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    \$\begingroup\$ A0 can be 1 or 0, which selects a specific column of 2. This must be done before a read via WL0 or WL2 (rows) for A0=1 (column) or WL1 or WL3 for A0=0. Now factor in 256 rows by 256 columns and you see how it scales. Address AND row select a specific FET but we must have column before row, so we access 1 FET of the column. \$\endgroup\$ Commented Jul 7 at 19:28

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There must be no more than one word line active at any given time; otherwise, there would be conflicts on the bit lines. Therefore, it is a requirement that the address be valid well before the active-low precharge pulse occurs. The precharge pulse is what drives exactly one word line active (high), and it stays that way after the pulse ends. It gets pulled low the next time the address changes.

"Valid" means that each of the address lines has a stable 1 or 0 value for the duration of the interval so labeled.

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  • \$\begingroup\$ Hi, thanks for the help. So in our case, regarding the valid, during the precharge, the valid has stable "1"? Also, in the graphs I gave, we see the valid bit is a little before the precharge, is it in purpose or just bad drawing? it should start before the precharge? \$\endgroup\$ Commented Jul 7 at 15:34
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    \$\begingroup\$ Yes, all address lines must be valid (not changing) before the precharge pulse starts. A proper design will have some timing margin here to allow for manufacturing variations. \$\endgroup\$ Commented Jul 7 at 15:47
  • \$\begingroup\$ Great, thank you very much!!! Mind if I ask something else? how will it be different if I was reading? Sorry for this not related question, I want to understand the difference. \$\endgroup\$ Commented Jul 7 at 15:53
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    \$\begingroup\$ This part of the memory architecture is the same for both reading and writing. The difference between reading and writing occurs on the bit lines. \$\endgroup\$ Commented Jul 7 at 17:04
  • \$\begingroup\$ Oh right, thanks!!! \$\endgroup\$ Commented Jul 7 at 17:17
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If the word lines are going directly to the rows of the DRAM array, what he's calling the "precharge" devices would need to be sized in such a way that any one of the pull-down transistors on the address lines could overpower them. Initially, all rows would need to start low, and then all rows other than the selected word would need to be prevented from rising even momentarily, thus making it necessary for the address wires to be valid before precharge is enabled.

An alternative design approach, which perhaps you were expecting, would be to have all address wires (true and complement) disabled while the precharge signal is pulsed (meaning all of the word lines in this schematic go high during the precharge phase), but have an extra layer of logic between the row lines shown here and the row lines of the actual array. I haven't studied VLSI design since 1994, but I would expect any practical designs to add an extra layer of buffering between the decode matrix and the row lines of the actual array, and having such buffering disable the outputs any time the address wasn't valid would impose less of a speed penalty than making the precharge devices weak enough to be reliably overdriven.

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  • \$\begingroup\$ I understand what you're saying about an alternative approach, but then you're presuming an awful lot of additional logic not in evidence. In the context of an exam question, you generally need to stick to only what is actually shown. \$\endgroup\$ Commented Jul 7 at 17:20
  • \$\begingroup\$ @DaveTweed: The word lines of the array will represent a fairly large capacitive load. In a device with even a 64x64 memory array, external latching would reduce the capacitive loading on the decoded outputs by more than an order of magnitude, reducing the required drive strength of the precharge transistors by a comparable amount. Further, precharging all the row outputs unopposed and then pulling down them all down unopposed would likely allow another order of magnitude current saving versus having all but one of the precharge outputs actively fighting the row decode logic. \$\endgroup\$ Commented Jul 8 at 17:24
  • \$\begingroup\$ @DaveTweed: Unless the course is intended to teach things from a historical perspective, and such techniques were in fact used with RAM arrays that were small enough to make them practical without row buffering, I'm not sure what the intention would be of showing a design approach that would have been impractical in the 1980s and become increasingly impractical with each succeeding decade. Some things can be cool without being practical (e.g. a full adder using two NPN transistors and carefully chosen resistors) but this design doesn't seem to fit that category. \$\endgroup\$ Commented Jul 8 at 18:03

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