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The algorithm is literally just squaring and reduction modulo some large n. That only requires the values of n, t (peanuts, a few thousand bits each). Perhaps the multiplication and modulo algorithms used require some tables, but if so you could probably hard-code them into the FPGA program.

user7043
– user7043

2014-05-21 15:47:33 +00:00
Commented May 21, 2014 at 15:47
@Dunk: thanks a lot, this helps me a lot. The 100x to 1000x ballpark is very interesting and so is your detailed explanation.

Cedric Martin
– Cedric Martin

2014-05-22 13:10:35 +00:00
Commented May 22, 2014 at 13:10

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