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improved test bench to make it easier to test more primes/non-primes

edited Mar 20, 2016 at 4:14

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The input n is an input port of the entity e; a natural number (starts at 0 for VHDL). b is an output port of entity e; a bit (meaning '1' or '0'). This works by the ever-famous method of trial division, with a special case for 1. This is what it looks like formatted nicely:

entity m is end; architecture a of m is signal i_n : natural := 2; signal i_b : bit; type int_vector is array(natural range<>) of natural; constant primes : int_vector := (2,3,5,7,11,13,17,19,23,29,31,37,41,43,47,53,59,61,67,71,73,79,83,89,97); function is_prime(n : natural) return boolean is begin for i in primes'range loop if n=primes(i) then return true; end if; end loop; return false;  end; begin x:entity work.e port map(n=>i_n, b=>i_b); process begin i_nfor <=i 1;in 1 to primes'right loop wait for 10ns;  i_n <= i;  assert i_b='0';  wait i_nfor <=10 2;ns; wait for 10ns; if is_prime(i) then   assert i_b='1'; i_n <= 3;  else  wait for 10ns;  assert i_b='1';i_b='0'; i_n <= 10;  end if;  wait for 10ns;  end loop;  assert i_b='0';  report "finished" severity error; -- error to reportstop "finished";simulation end process; end a;

This is the result.This is the result.

The input n is an input port of the entity e; a natural number (starts at 0 for VHDL). b is an output port of entity e; a bit (meaning '1' or '0'). This is what it looks like formatted nicely:

entity m is end; architecture a of m is signal i_n : natural := 2; signal i_b : bit; begin x:entity work.e port map(n=>i_n, b=>i_b); process begin i_n <= 1; wait for 10ns;  assert i_b='0';  i_n <= 2; wait for 10ns; assert i_b='1'; i_n <= 3;  wait for 10ns;  assert i_b='1'; i_n <= 10;  wait for 10ns;  assert i_b='0';  report "finished"; end process; end a;

This is the result.

entity m is end; architecture a of m is signal i_n : natural := 2; signal i_b : bit; type int_vector is array(natural range<>) of natural; constant primes : int_vector := (2,3,5,7,11,13,17,19,23,29,31,37,41,43,47,53,59,61,67,71,73,79,83,89,97); function is_prime(n : natural) return boolean is begin for i in primes'range loop if n=primes(i) then return true; end if; end loop; return false;  end; begin x:entity work.e port map(n=>i_n, b=>i_b); process begin for i in 1 to primes'right loop i_n <= i;  wait for 10 ns;  if is_prime(i) then   assert i_b='1'; else  assert i_b='0'; end if;  end loop;  report "finished" severity error; -- error to stop simulation end process; end a;

This is the result.

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answered Mar 20, 2016 at 4:03

Justin

21.4k
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VHDL, 236 bytes

entity e is port(n:natural;b:out bit);end;architecture a of e is function p(n:natural)return bit is begin if n=1 then return'0';end if;for i in 2 to n-1 loop if n mod i=0 then return'0';end if;end loop;return'1';end;begin b<=p(n);end a;

entity e is port( n : in natural; b : out bit); end; architecture a of e is function p(n:natural) return bit is begin if n=1 then return '0'; end if; for i in 2 to n-1 loop if n mod i=0 then return '0'; end if; end loop; return'1'; end; begin b<=p(n); end a;

Here's the testbench I used for verification:

entity m is end; architecture a of m is signal i_n : natural := 2; signal i_b : bit; begin x:entity work.e port map(n=>i_n, b=>i_b); process begin i_n <= 1; wait for 10ns; assert i_b='0'; i_n <= 2; wait for 10ns; assert i_b='1'; i_n <= 3; wait for 10ns; assert i_b='1'; i_n <= 10; wait for 10ns; assert i_b='0'; report "finished"; end process; end a;

This is the result.