Timeline for About hardware multithreading
Current License: CC BY-SA 4.0
7 events
| when toggle format | what | by | license | comment | |
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| May 30 at 10:29 | comment | added | gnasher729 | So you wouldn't double the expensive parts. You only double what needs doubling: Named registers (but you just take them out of your rename registers), and the instruction decoder, since you obviously need to parse two instructions. If you were willing to double the cost, you'd add another core. Hyperthreading should give you some more instructions at minimal added cost. And the worse your single threaded code is, the more it helps. | |
| May 30 at 10:26 | comment | added | gnasher729 | A single core could process so many instructions per cycle with optimal code, but the code is usually not optimal. Hyperthreading allows a second thread to slot into the unused places in the pipeline. Say you could in theory do four ops per cycle, but your code does only three. Then another hyperthread can use the one unused op, so your two threads do 4 ops per cycle. That's only a little bit of added performance, but at minimal added cost. | |
| Dec 8, 2018 at 7:13 | comment | added | Pseudonym♦ | The main cost isn't a doubling of the number of registers on a modern CPU. The main cost is a doubling of the issue/retirement logic. The reorder buffer, in particular, is one of the most power-hungry parts of a modern CPU. | |
| Dec 8, 2018 at 2:39 | comment | added | Kindred | From your "The main cost is a doubling of the number of registers", then my second comment on this answer is incorrect? | |
| Dec 8, 2018 at 2:36 | vote | accept | Kindred | ||
| Dec 7, 2018 at 10:48 | comment | added | Kindred | But in many instruction streams there isn’t: I haven't learned about this phrase, does it mean the possible sequence of instructions? | |
| Dec 7, 2018 at 10:20 | history | answered | Martin Kochanski | CC BY-SA 4.0 |