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Signal Processing

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  • $\begingroup$ I have to admit that I didn't solve each of your equations given but I see your general question is concern about the bits and rounding in an FIR filter. It is very important for noise considerations to let the filter grow the signal and then truncate the signal after. i detail this further in these posts which may interest you: dsp.stackexchange.com/questions/31577/inter-filter-bit-width/… dsp.stackexchange.com/questions/38620/… $\endgroup$ Commented May 12, 2021 at 1:30
  • $\begingroup$ thanks for the links. I would add that besides noise considerations in the first link, more important to me is power consumption. Adding more bits is not desired in my case. So my design flow is somewhat different than the flow shown in the second link $\endgroup$ Commented May 12, 2021 at 1:59
  • $\begingroup$ I would respectfully argue it is the same; as you want to minimize the total number of bits within some SNR or other requirements constraint; so this informs the least you can add within that constraint. Further you would be very interested then in multi-rate signal processing as power is a major motivator for that (minimizing the sampling rate wherever possible since dynamic power goes as $C V^2 f$ $\endgroup$ Commented May 12, 2021 at 2:05
  • $\begingroup$ Most importantly is to not naively think you can just scale the coefficients to prevent overflow without considering the total quantization noise growth. That is my point. $\endgroup$ Commented May 12, 2021 at 2:06
  • $\begingroup$ yeah, I understand your point of reaching optimal SNR when selecting coefficient bitwidth. That is a different starting point than my question though: I meant the coefficients are already given, can't change them. So what else can be done other than the simulation wave shown below to decide intermediate results' bitwidth? $\endgroup$ Commented May 12, 2021 at 2:08