Timeline for Problem in synthesizing
Current License: CC BY-SA 3.0
15 events
| when toggle format | what | by | license | comment | |
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| Apr 28, 2014 at 14:54 | comment | added | ajs410 | 1) Are you setting clr to 1 after the initial clock pulse during your test? if it stays at 1, the if clk edge never "wins" 2) You do not need the elsif CLR='1', it is implicit because otherwise we would take the if CLR='0' path 3) You should generally avoid inout except when instantiating top-level bidirectional buses, use out in the port declaration and use signals internally, e.g. signal q_int : std_logic_vector(3 downto 0); and at the bottom, Q <= q_int; 4) The better way to handle this rotation would be q_int <= q_int(2 downto 0) & q_int(3) inside the if clk edge. | |
| Apr 27, 2014 at 6:03 | history | edited | user40295 | CC BY-SA 3.0 | added 1501 characters in body |
| Apr 25, 2014 at 19:49 | answer | added | ajs410 | timeline score: 1 | |
| Apr 25, 2014 at 10:17 | history | edited | user40295 | CC BY-SA 3.0 | added 471 characters in body |
| S Apr 24, 2014 at 17:25 | history | suggested | fru1tbat | CC BY-SA 3.0 | reformatted |
| Apr 24, 2014 at 16:59 | comment | added | fru1tbat | on your edit - have you specified a reset? Initializing the q3 signal at the declaration won't do anything for simulation as it is driven by a DFF instance. | |
| Apr 24, 2014 at 16:58 | review | Suggested edits | |||
| S Apr 24, 2014 at 17:25 | |||||
| Apr 24, 2014 at 16:08 | history | edited | user40295 | CC BY-SA 3.0 | added 1427 characters in body |
| Apr 24, 2014 at 12:42 | answer | added | fru1tbat | timeline score: 0 | |
| S Apr 24, 2014 at 12:22 | history | suggested | fru1tbat | CC BY-SA 3.0 | split blockquote from non-quote text, replace '<' with '<' in non-html text |
| Apr 24, 2014 at 12:19 | review | Suggested edits | |||
| S Apr 24, 2014 at 12:22 | |||||
| Apr 24, 2014 at 9:31 | answer | added | apalopohapa | timeline score: 3 | |
| Apr 24, 2014 at 9:17 | comment | added | Dean | Could you be more specific to where the error has come from - what tool are you using Xilinx ISE or Altera Quartus or similar. | |
| Apr 24, 2014 at 9:15 | history | edited | Dean | CC BY-SA 3.0 | Added formatting |
| Apr 24, 2014 at 8:19 | history | asked | user40295 | CC BY-SA 3.0 |