Timeline for Decoupling caps, PCB layout
Current License: CC BY-SA 4.0
23 events
| when toggle format | what | by | license | comment | |
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| Feb 16 at 4:07 | comment | added | Mike DeSimone | The world has changed since this post… Now we have boards with HDI (laser) vias, and it’s actually a viable strategy to make the surface layers ground layers. This reduces inductance even more, because the ground leg of each decoupling capacitor no longer has series via inductance! | |
| Feb 6 at 1:22 | comment | added | Jim J. Jewett | @richieqianle One thing I didn't catch the first few times I read this is that Olin wasn't actually splitting the plane. Until today, I would have wrongly assumed he was making a hole the size of the local plane, plus the separation. Instead he added an extra smaller plane on an even closer layer, but still kept the main plane unbroken -- including under the small local plane. | |
| Jan 29, 2021 at 11:17 | history | edited | Ariser | CC BY-SA 4.0 | Formatting and greek symbols. |
| Jan 8, 2021 at 16:24 | history | edited | Mike DeSimone | CC BY-SA 4.0 | Prefer mm to cm, space required between a number and its units, and when showing alternate units, enclose in brackets. |
| S Jan 7, 2021 at 17:26 | history | suggested | pfabri | CC BY-SA 4.0 | Added SI unit to ease understanding |
| Jan 7, 2021 at 15:57 | review | Suggested edits | |||
| S Jan 7, 2021 at 17:26 | |||||
| Jun 11, 2020 at 15:10 | history | edited | CommunityBot | Commonmark migration | |
| Jun 25, 2014 at 10:45 | comment | added | richieqianle | Thank you very much! Your comments make a lot of sense. :) | |
| Jun 24, 2014 at 17:03 | comment | added | Mike DeSimone | Also, if you're splitting the ground plane, you need to split the power planes at the same place. Remember, at AC frequencies, power and ground are effectively the same potential (if properly decoupled), and field lines will act accordingly. | |
| Jun 24, 2014 at 16:59 | comment | added | Mike DeSimone | Split planes are tricky. You can wind up creating EMI problems where they weren't before if you're not careful. Also you can compromise the low impedance of a plane if you split it into too-small pieces, like strips. Henry Ott recommends against it, arguing that component placement and layout can often achieve better performance than split planes would give. That said, there are cases where they make sense, but you need to treat the split plane similar to a plugged-in mezzanine card, with its own decoupling and such near the single point of connection, and forbid traces crossing the split. | |
| Jun 24, 2014 at 7:34 | comment | added | richieqianle | He suggested to connect the grounds together and then connect with the main power frame at a single point. The technique is essentially split plane I think, which is not recommended in your post. | |
| Jun 23, 2014 at 15:57 | comment | added | Mike DeSimone | Contradiction how? | |
| Jun 23, 2014 at 14:27 | comment | added | richieqianle | It seems that the answer from @Olin Lathrop is in contradiction with this one.. | |
| Jun 27, 2013 at 14:16 | comment | added | Mike DeSimone | The extremely low inductance of power and ground planes changed all the rules, by making the inductance getting to the plane far more important than inductance due to position on the plane. Thus the "near the part" requirement is obsolete in most cases (basically, any case where your power plane is small enough not to have transmission line effects), and the limiting factor is the inductance from the capacitor's packaging and how its vias are routed to the planes, and the same for the chip. So many chip manufacturers are adding power pins to reduce inductance, not because they need more caps. | |
| Jun 27, 2013 at 14:12 | comment | added | Mike DeSimone | The "one 0.1 uF cap per power pin" is a rule of thumb dating back to the days of DIPs and two-layer boards with no power or ground planes. In those cases, you would get a significant amount of inductance just getting power to each chip, most chips only had one or two power pins, and 0.01 uF capacitors wouldn't help much because their decoupling would be defeated by the inductance of the lead frame in the part. | |
| Jun 27, 2013 at 14:09 | comment | added | Mike DeSimone | @vicatcu: It's from Bogatin's book, Signal Integrity Simplified, and also covered by his webinar on PDN design. BTW, the only real "counterproductivity" is that 1) in a high-speed design it might be insufficient, especially if there's a band that isn't sufficiently covered by the 0.1 uF caps, and 2) it's more likely that you don't need nearly that many capacitors given the high number of power pins on modern chips. You can also work with Altera's PDN tool to see these effects. | |
| Jun 26, 2013 at 18:44 | comment | added | vicatcu | @MikeDeSimone please can you give a direct links to articles concerning the counterproductivity of the "one 0.1 uF capacitor per power pin" strategy? | |
| Jul 12, 2012 at 23:54 | comment | added | Tony Stewart EE since 1975 | Everything you need to know about EMC was written in Henry Ott's book in your link. Anyone who wants to really master EMC needs to read it. Shielding, filtering, coupling vs decoupling, orientation, material effects, ferrites, shapes and other non-ideal characteristics. common central grounds, distributed all need low ESR, low inductance, visualizing the antenna effects in structures on PCB, chassis and interface cables, ESR, wavelengths, prop. delays, crosstalk, impedance controls, isolating analog ground from digital grounds, guarding methods, Common filtering, differential mode, etc etc | |
| Jun 10, 2011 at 14:21 | comment | added | Mike DeSimone | And one more thing: something that also sneaks in is skin effect. (Yes, even a 1 oz. copper plane has skin effect at high speeds.) If you have a trace go between two planes that are next to the same reference plane, you're safe because the return current path on that reference plane can follow the hole in the plane made for the via. If you jump between layers that have different reference planes, though, the return current has to find a path between the reference planes. Usually this is a nearby ground via connecting both planes, but sometimes you'll need to add a stitching via. | |
| Jun 10, 2011 at 14:12 | comment | added | Mike DeSimone | It's kind of like programming: while optimizing code that runs only once or a few times will technically make the program run faster, it's not nearly as much benefit per hour effort as optimizing the code that gets called a lot, say in loops. Before I forget, there's one more thing: a reference plane typically has capacitance with a power plane, reducing its impedance to even less than trace and via impedance, but it might not be that big of a difference (1 nF/sqft or so?). | |
| Jun 10, 2011 at 14:08 | comment | added | Mike DeSimone | @morten: yeah, that knocked me silly the first time I read it in Altera's materials, too. But it's a provable thing: if you look at the inductance component injected by the plane itself, it is actually small when compared to the inductance of the vias, traces, and component packaging. You'll need to break out vector calculus and Maxwell's Equations to prove it exactly, but if you can visualize it, the basic idea is that the magnetic field around a plane is weaker than around a wire (via or trace) due to its geometry. A weaker magnetic field means lower inductance. | |
| Jun 9, 2011 at 8:21 | comment | added | morten | Thanks, your answer has led me deep into unknown territory! One thing that is confusing is "the distance from load to decoupling capacitor does not matter" when the reference plane is considered a lumped node. This seems to go against everything else said. | |
| Jun 8, 2011 at 15:13 | history | answered | Mike DeSimone | CC BY-SA 3.0 |