Timeline for timing constraint for bus synchronizer circuits
Current License: CC BY-SA 3.0
13 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| S Aug 17, 2017 at 13:55 | history | suggested | user154136 | Added [sdc] tag | |
| Aug 17, 2017 at 13:49 | review | Suggested edits | |||
| S Aug 17, 2017 at 13:55 | |||||
| Jun 24, 2011 at 16:38 | vote | accept | Ben Voigt | ||
| Jun 16, 2011 at 16:52 | answer | added | Andy | timeline score: 12 | |
| Jun 16, 2011 at 16:42 | answer | added | fbo | timeline score: 0 | |
| Jun 16, 2011 at 15:38 | answer | added | supercat | timeline score: 0 | |
| Jun 16, 2011 at 13:12 | answer | added | user3624 | timeline score: 1 | |
| Jun 16, 2011 at 5:27 | comment | added | Ben Voigt | @Andy: I added some of the details. Thanks for helping with this. | |
| Jun 16, 2011 at 5:23 | history | edited | Ben Voigt | CC BY-SA 3.0 | added 210 characters in body; added 127 characters in body |
| Jun 16, 2011 at 5:02 | comment | added | Andy | Can you post the clock definitions for src_clk and dest_clk? Are they related in any way (synchronous multiples)? If they're unrelated clocks then it's typical to use set_false_path in this situation. | |
| Jun 15, 2011 at 23:45 | history | tweeted | twitter.com/#!/StackElectronix/status/81145408621002752 | ||
| Jun 15, 2011 at 21:30 | comment | added | Ben Voigt | This would be better on the proposed FPGA Design site but that proposal hasn't reached beta yet. | |
| Jun 15, 2011 at 21:25 | history | asked | Ben Voigt | CC BY-SA 3.0 |