Timeline for timing constraint for bus synchronizer circuits
Current License: CC BY-SA 3.0
3 events
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| Aug 31, 2012 at 15:03 | comment | added | supercat | @BenVoigt: I think "set_multicycle_path" is more often used to tell the timing validator that a chain of combinatorial logic between two latching points should be allowed to take N(Tc)-Ts-Tp (N times cycle time minus sample time minus latch propagation time) instead of just Tc-Ts-Th. I don't know how such a thing would interact with latching by different clocks. | |
| Jun 16, 2011 at 15:45 | comment | added | Ben Voigt | Wouldn't set_multicycle_path be the way to tell the synthesizer/timing analyzer how often the source signals can change? And I'm not sure what you mean by "bus clock", there's a signal bus here crossing clock domains, so which clock are you calling the "bus clock"? I think you're right that there still could be metastability if the synthesizer introduces glitches during periods when I'm not updating data. I guess I could specifically instantiate DFF blocks there :( | |
| Jun 16, 2011 at 15:38 | history | answered | supercat | CC BY-SA 3.0 |