Timeline for VHDL Block RAM Inference
Current License: CC BY-SA 3.0
10 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| May 4, 2015 at 6:43 | comment | added | Sai Gautam | @FarhadA yes...have done it | |
| Apr 30, 2015 at 6:36 | comment | added | FarhadA | What you have in here is giant combinatorial block you need to synchronize your access by putting the read operation in the clocked process. | |
| Apr 29, 2015 at 18:42 | history | tweeted | twitter.com/#!/StackElectronix/status/593485542634946562 | ||
| Apr 29, 2015 at 14:22 | answer | added | Martin Thompson | timeline score: 2 | |
| Apr 29, 2015 at 14:20 | history | edited | Martin Thompson | CC BY-SA 3.0 | added 6 characters in body |
| Apr 29, 2015 at 8:01 | answer | added | alex.forencich | timeline score: 3 | |
| Apr 29, 2015 at 7:56 | history | edited | Sai Gautam | CC BY-SA 3.0 | added 1486 characters in body |
| Apr 29, 2015 at 7:46 | comment | added | Sai Gautam | I will modify the question to add code.. | |
| Apr 29, 2015 at 7:24 | comment | added | Paebbels | Can you present some code? You can set a RAM_STYLE attribute to force BlockRAM usage. I assume XST misses a read clock because BlockRAM does not support synchronous read. | |
| Apr 29, 2015 at 7:05 | history | asked | Sai Gautam | CC BY-SA 3.0 |