Timeline for VHDL Block RAM Inference
Current License: CC BY-SA 3.0
9 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Apr 29, 2015 at 11:39 | comment | added | Sai Gautam | It works now...I had some timing issues but now no more. Thank you very much! | |
| Apr 29, 2015 at 9:41 | comment | added | alex.forencich | You can register it again later if you need to, but it has to be registered at the same time you do the lookup for it to infer a block RAM. | |
| Apr 29, 2015 at 8:51 | comment | added | Sai Gautam | i however saw that if i register the output inside a simple clocked process, the tool infers a block ram | |
| Apr 29, 2015 at 8:50 | comment | added | Sai Gautam | i want the output to be registered based on the 2 MSBs of the counter. So I have a case statement inside the process where the output is being registered. this is a clocked process | |
| Apr 29, 2015 at 8:49 | comment | added | Sai Gautam | i registered the output. It still doesnt work. | |
| Apr 29, 2015 at 8:07 | comment | added | alex.forencich | Yeah. Xilinx block RAMs want a register on the output data. If you don't provide one, this is the error you get. Yes, I have made this mistake many times before. | |
| Apr 29, 2015 at 8:06 | history | edited | alex.forencich | CC BY-SA 3.0 | added 339 characters in body |
| Apr 29, 2015 at 8:04 | comment | added | Sai Gautam | u mean i should register cos assignment as well? | |
| Apr 29, 2015 at 8:01 | history | answered | alex.forencich | CC BY-SA 3.0 |