Return to Question

deleted 4 characters in body; edited title

edited Sep 15, 2022 at 22:31

9.4k
23
33
43

Verilog: Slow Clock Generator Moduleslow clock generator module (1Hz1 Hz from 50MHz50 MHz)

I wrote a clock generator module. I think the problem is in my Reg4Reg4 module. The errors are:

ERROR:HDLCompilers:246 - "UpDownCounter.v" line 74 Reference to scalar reg 'clk_1Hz' is not a legal net lvalue

ERROR:HDLCompilers:102 - "UpDownCounter.v" line 74 Connection to output port 'clk_1Hz' must be a net lvalue

1 Hz Clock Generatorclock generator:

module slowClock(clk, reset, clk_1Hz); input clk, reset; output clk_1Hz; reg clk_1Hz = 1'b0; reg [27:0] counter; always@(posedge reset or posedge clk) begin if (reset == 1'b1) begin clk_1Hz <= 0; counter <= 0; end else begin counter <= counter + 1; if ( counter == 25_000_000) begin counter <= 0; clk_1Hz <= ~clk_1Hz; end end end endmodule

Here is my Reg4Reg4 bit module:

module Reg4(I, Q, clk, reset); input clk, reset; input [3:0] I; output [3:0] Q; reg [3:0] Q; reg clk_1Hz = 1'b0; slowClock clock_generator(clk, reset, clk_1Hz); always@(posedge clk_1Hz) begin if (reset == 1) Q <= 4'b0000; else Q <= I; end endmodule

Can you see the problem in my code?

Verilog: Slow Clock Generator Module (1Hz from 50MHz)

I wrote a clock generator module. I think the problem is in my Reg4 module. The errors are:

ERROR:HDLCompilers:246 - "UpDownCounter.v" line 74 Reference to scalar reg 'clk_1Hz' is not a legal net lvalue

ERROR:HDLCompilers:102 - "UpDownCounter.v" line 74 Connection to output port 'clk_1Hz' must be a net lvalue

1 Hz Clock Generator:

module slowClock(clk, reset, clk_1Hz); input clk, reset; output clk_1Hz; reg clk_1Hz = 1'b0; reg [27:0] counter; always@(posedge reset or posedge clk) begin if (reset == 1'b1) begin clk_1Hz <= 0; counter <= 0; end else begin counter <= counter + 1; if ( counter == 25_000_000) begin counter <= 0; clk_1Hz <= ~clk_1Hz; end end end endmodule

Here is my Reg4 bit module:

module Reg4(I, Q, clk, reset); input clk, reset; input [3:0] I; output [3:0] Q; reg [3:0] Q; reg clk_1Hz = 1'b0; slowClock clock_generator(clk, reset, clk_1Hz); always@(posedge clk_1Hz) begin if (reset == 1) Q <= 4'b0000; else Q <= I; end endmodule

Can you see the problem in my code?

Verilog: slow clock generator module (1 Hz from 50 MHz)

I wrote a clock generator module. I think the problem is in my Reg4 module. The errors are:

ERROR:HDLCompilers:246 - "UpDownCounter.v" line 74 Reference to scalar reg 'clk_1Hz' is not a legal net lvalue

ERROR:HDLCompilers:102 - "UpDownCounter.v" line 74 Connection to output port 'clk_1Hz' must be a net lvalue

1 Hz clock generator:

module slowClock(clk, reset, clk_1Hz); input clk, reset; output clk_1Hz; reg clk_1Hz = 1'b0; reg [27:0] counter; always@(posedge reset or posedge clk) begin if (reset == 1'b1) begin clk_1Hz <= 0; counter <= 0; end else begin counter <= counter + 1; if ( counter == 25_000_000) begin counter <= 0; clk_1Hz <= ~clk_1Hz; end end end endmodule

Here is my Reg4 bit module:

module Reg4(I, Q, clk, reset); input clk, reset; input [3:0] I; output [3:0] Q; reg [3:0] Q; reg clk_1Hz = 1'b0; slowClock clock_generator(clk, reset, clk_1Hz); always@(posedge clk_1Hz) begin if (reset == 1) Q <= 4'b0000; else Q <= I; end endmodule

Can you see the problem in my code?

added 4 characters in body; edited title

Source Link

edited Sep 15, 2022 at 19:53

toolic

10.9k
11
31
35

Verilog: Slow Clock GeneatorGenerator Module (1Hz from 50Mhz50MHz)

I wrote a clock generator module, i dont know if it is true but. I think the problem is in my regReg4 module. The error is:

ERROR:HDLCompilerserrors are:246 - "UpDownCounter.v" line 74 Reference to scalar reg 'clk_1Hz' is not a legal net lvalue

ERROR:HDLCompilers:102 - "UpDownCounter.v" line 74 Connection to output port 'clk_1Hz' must be a net lvalue

ERROR:HDLCompilers:246 - "UpDownCounter.v" line 74 Reference to scalar reg 'clk_1Hz' is not a legal net lvalue

ERROR:HDLCompilers:102 - "UpDownCounter.v" line 74 Connection to output port 'clk_1Hz' must be a net lvalue

1 HZ CLOCK GENERATORHz Clock Generator:

module slowClock(clk, reset, clk_1Hz); input clk, reset; output clk_1Hz; reg clk_1Hz = 1'b0; reg [27:0] counter; always@(posedge reset or posedge clk) begin if (reset == 1'b1) begin clk_1Hz <= 0; counter <= 0; end else begin counter <= counter + 1; if ( counter == 25_000_000) begin counter <= 0; clk_1Hz <= ~clk_1Hz; end end end endmodule

And hereHere is my Reg 4Reg4 bit module:

module Reg4(I, Q, clk, reset); input clk, reset; input [3:0] I; output [3:0] Q; reg [3:0] Q;   reg clk_1Hz = 1'b0; slowClock clock_generator(clk, reset, clk_1Hz); always@(posedge clk_1Hz) begin if (reset == 1) Q <= 4'b0000; else Q <= I;   end endmodule

Can uyou see mythe problem in my code? :(

Verilog: Slow Clock Geneator Module (1Hz from 50Mhz)

I wrote clock generator module, i dont know if it is true but the problem is in my reg module. The error is:

ERROR:HDLCompilers:246 - "UpDownCounter.v" line 74 Reference to scalar reg 'clk_1Hz' is not a legal net lvalue

ERROR:HDLCompilers:102 - "UpDownCounter.v" line 74 Connection to output port 'clk_1Hz' must be a net lvalue

1 HZ CLOCK GENERATOR

module slowClock(clk, reset, clk_1Hz); input clk, reset; output clk_1Hz; reg clk_1Hz = 1'b0; reg [27:0] counter; always@(posedge reset or posedge clk) begin if (reset == 1'b1) begin clk_1Hz <= 0; counter <= 0; end else begin counter <= counter + 1; if ( counter == 25_000_000) begin counter <= 0; clk_1Hz <= ~clk_1Hz; end end end endmodule

And here my Reg 4 bit module

module Reg4(I, Q, clk, reset); input clk, reset; input [3:0] I; output [3:0] Q; reg [3:0] Q;   reg clk_1Hz = 1'b0; slowClock clock_generator(clk, reset, clk_1Hz); always@(posedge clk_1Hz) begin if (reset == 1) Q <= 4'b0000; else Q <= I;   end endmodule

Can u see my problem ? :(

Verilog: Slow Clock Generator Module (1Hz from 50MHz)

I wrote a clock generator module. I think the problem is in my Reg4 module. The errors are:

ERROR:HDLCompilers:246 - "UpDownCounter.v" line 74 Reference to scalar reg 'clk_1Hz' is not a legal net lvalue

ERROR:HDLCompilers:102 - "UpDownCounter.v" line 74 Connection to output port 'clk_1Hz' must be a net lvalue

1 Hz Clock Generator:

module slowClock(clk, reset, clk_1Hz); input clk, reset; output clk_1Hz; reg clk_1Hz = 1'b0; reg [27:0] counter; always@(posedge reset or posedge clk) begin if (reset == 1'b1) begin clk_1Hz <= 0; counter <= 0; end else begin counter <= counter + 1; if ( counter == 25_000_000) begin counter <= 0; clk_1Hz <= ~clk_1Hz; end end end endmodule

Here is my Reg4 bit module:

module Reg4(I, Q, clk, reset); input clk, reset; input [3:0] I; output [3:0] Q; reg [3:0] Q; reg clk_1Hz = 1'b0; slowClock clock_generator(clk, reset, clk_1Hz); always@(posedge clk_1Hz) begin if (reset == 1) Q <= 4'b0000; else Q <= I; end endmodule

Can you see the problem in my code?

Source Link

asked Dec 6, 2015 at 0:21

funky-nd

Verilog: Slow Clock Geneator Module (1Hz from 50Mhz)

I wrote clock generator module, i dont know if it is true but the problem is in my reg module. The error is:

ERROR:HDLCompilers:246 - "UpDownCounter.v" line 74 Reference to scalar reg 'clk_1Hz' is not a legal net lvalue

ERROR:HDLCompilers:102 - "UpDownCounter.v" line 74 Connection to output port 'clk_1Hz' must be a net lvalue

1 HZ CLOCK GENERATOR

module slowClock(clk, reset, clk_1Hz); input clk, reset; output clk_1Hz; reg clk_1Hz = 1'b0; reg [27:0] counter; always@(posedge reset or posedge clk) begin if (reset == 1'b1) begin clk_1Hz <= 0; counter <= 0; end else begin counter <= counter + 1; if ( counter == 25_000_000) begin counter <= 0; clk_1Hz <= ~clk_1Hz; end end end endmodule

And here my Reg 4 bit module

module Reg4(I, Q, clk, reset); input clk, reset; input [3:0] I; output [3:0] Q; reg [3:0] Q; reg clk_1Hz = 1'b0; slowClock clock_generator(clk, reset, clk_1Hz); always@(posedge clk_1Hz) begin if (reset == 1) Q <= 4'b0000; else Q <= I; end endmodule

Can u see my problem ? :(