Timeline for How can I show a tied-off output on a digital logic schematic?
Current License: CC BY-SA 3.0
7 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Jun 11, 2020 at 15:10 | history | edited | CommunityBot | Commonmark migration | |
| Jan 20, 2016 at 21:53 | history | edited | Adam Haun | CC BY-SA 3.0 | Clarified the title |
| Jan 20, 2016 at 17:10 | answer | added | Aadarsh | timeline score: 1 | |
| Jan 20, 2016 at 17:00 | comment | added | Jakub Rakus | You have mistakes in truth table, and so in equations and on schematic. Check once again how to calculate 2's and 1's complement. | |
| Jan 20, 2016 at 16:45 | comment | added | Marco | Since the three inputs have no effect on D you can just tie it to zero. It would be even better to just leave it out. btw I didn't look at the correctness of the equations. | |
| Jan 20, 2016 at 16:45 | review | First posts | |||
| Jan 20, 2016 at 16:53 | |||||
| Jan 20, 2016 at 16:42 | history | asked | user97720 | CC BY-SA 3.0 |