Timeline for Do I need to reset my FPGA design after startup?
Current License: CC BY-SA 3.0
11 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Feb 13, 2024 at 4:01 | answer | added | Bill | timeline score: 0 | |
| Apr 15, 2016 at 15:08 | vote | accept | Martin Zabel | ||
| Apr 15, 2016 at 2:28 | history | tweeted | twitter.com/StackElectronix/status/720800886977601538 | ||
| Apr 14, 2016 at 14:45 | answer | added | Martin Zabel | timeline score: 4 | |
| Apr 13, 2016 at 8:02 | history | edited | Martin Zabel | CC BY-SA 3.0 | better explanation of the purpose of the example |
| Apr 12, 2016 at 19:02 | comment | added | Martin Zabel | @KrunalDesai The white-paper actually states that no user-defined reset is required because flip-flops and so on are reseted to ther initial value during configuration. But this contradicts the footnote cited in my question: It is recommended to reset the design after startup and/or apply some other synchronization technique. | |
| Apr 12, 2016 at 18:13 | answer | added | davidd | timeline score: 4 | |
| Apr 12, 2016 at 16:51 | comment | added | Krunal Desai | Austin Lesea is the guy from Xilinx to answer this I think, I remember reading an app note he either wrote or recommended that explains this -- ah yeah, here is the one: xilinx.com/support/documentation/white_papers/wp272.pdf | |
| Apr 12, 2016 at 15:39 | comment | added | WhatRoughBeast | A general rule - do not count on things which you do not control. If your startup state is important, provide an external reset which will release after configuration is complete. | |
| Apr 12, 2016 at 14:30 | history | edited | Martin Zabel | CC BY-SA 3.0 | changed example to ring counter |
| Apr 12, 2016 at 14:17 | history | asked | Martin Zabel | CC BY-SA 3.0 |