The schematic with the series resistor, and with a resistor to VSS and a cap to VDD is almost right, except that the cap should go to VSS (R2 most likely should do so as well). I would suggest starting by arbitrarily selecting 1K as a series resistor, and choosing R2 such that then the output from the RF receiver is at half-rail, the input to the processor will be near its switching point. A value of 2.2K for R2 should probably be good if the processor switches at around VDD/3. THe precise value probably won't matter too much. In any case, compute the effective parallel resistance of the two resistors together by taking the reciprocal of each, adding those values, and taking the reciprocal of the result. With the values given, 1/(1/1000 + 1/2200) = 687.5 ohms.

Next, figure out the fastest signal transitions you're interested in. Let's say you're interested in Manchester-encoded data sent at 100,000 bits/second. Since Manchester-coded data requires two signal transitions per bit, the time per transition would be a minimum of 5us. Divide the computed time (e.g. 5 microseconds) by the computed resistance (e.g. 687.5 ohms) to yield an approximate required capacitance value (in this case, roughly 0.0072 microfards). It's probably better for your cap to be a little small than too big; experiment and see what you get.

The schematic with the series resistor, and with a resistor to VSS and a cap to VDD is almost right, except that the cap should go to VSS (R2 most likely should do so as well). I would suggest starting by arbitrarily selecting 1K as a series resistor, and choosing R2 such that then the output from the RF receiver is at half-rail, the input to the processor will be near its switching point. A value of 2.2K for R2 should probably be good if the processor switches at around VDD/3. THe precise value probably won't matter too much. In any case, compute the effective parallel resistance of the two resistors together by taking the reciprocal of each, adding those values, and taking the reciprocal of the result. With the values given, 1/(1/1000 + 1/2200) = 687.5 ohms.

Next, figure out the fastest signal transitions you're interested in. Let's say you're interested in Manchester-encoded data sent at 100,000 bits/second. Since Manchester-coded data requires two signal transitions per bit, the time per transition would be a minimum of 5us. Divide the computed time (e.g. 5 microseconds) by the computed resistance (e.g. 687.5 ohms) to yield an approximate required capacitance value (in this case, roughly 0.0072 microfards). It's probably better for your cap to be a little small than too big; experiment and see what you get.

Addendum

If the sender and receiver will both have crystal-controlled bit rates, I'd suggest putting the signal through an analog filter circuit, and using an ADC to sample the output of the filter at 10Khz. Put the incoming signal into a rolling buffer long enough to handle the whole packet, and also use a 32-bucket accumulator to sum the difference between the present signal and the signal 384 samples ago (so the first difference gets added to bucket #0, the second to bucket #1, the 32nd to bucket #31, the 33rd to bucket #0, etc.). There should be two consecutive buckets with a huge difference between them (the later bucket having a much higher value than the previous). When that difference is spotted, that will indicate that one has found the rising edge of a pulse. At that point, one should be able to sum together groups of four samples from the original signal and recover the signal levels at those points.