Timeline for How can I generate a schematic block diagram image file from verilog?
Current License: CC BY-SA 4.0
3 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| S Dec 5, 2022 at 6:56 | history | suggested | trombonedude | CC BY-SA 4.0 | link to yosys was out of date and redirected to a shady german gambing website |
| Dec 5, 2022 at 0:17 | review | Suggested edits | |||
| S Dec 5, 2022 at 6:56 | |||||
| Nov 13, 2016 at 20:45 | history | answered | Marcus Müller | CC BY-SA 3.0 |