Timeline for What is the difference between DCM and PLL in e.g. Xilinx FPGA?
Current License: CC BY-SA 3.0
5 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Nov 16, 2016 at 11:09 | vote | accept | EquipDev | ||
| Nov 16, 2016 at 11:09 | comment | added | EquipDev | Thanks, very useful, and great rule to use the cheap resources (DCM) first where possible, and then the more expensive and versatile (PLL) is required. | |
| Nov 16, 2016 at 10:41 | comment | added | user16324 | Well, if you need jitter attenuation or you need to track a varying clock, you need the PLL. Also, DCMs usually have a low frequency limit (where the one cycle delay falls off the end of the delay line!) so slow clocks need a PLL. General rule is, use the DCM where it'll do the job, use PLL where you need it. | |
| Nov 16, 2016 at 10:34 | comment | added | EquipDev | Thanks for the detailed technical description; that is very useful to understanding the technology and uses. Are there any situations where DCM should be used instead of PLL, or vice versa, or is it more a question about use the one where e.g. jitter and freq. will ensure timing closure? | |
| Nov 16, 2016 at 10:24 | history | answered | user16324 | CC BY-SA 3.0 |