Timeline for Am I over-complicating this data acquisition design?
Current License: CC BY-SA 3.0
11 events
| when toggle format | what | by | license | comment | |
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| Jan 12, 2017 at 19:47 | comment | added | Marcus Müller | Maybe simply use a >= 16-channel ADC-containing ARM like this fairly solder friendly one: eu.mouser.com/ProductDetail/NXP-Semiconductors/LPC1517JBD64E/… | |
| Jan 12, 2017 at 18:05 | comment | added | Marcus Müller | So, for 16x 200Hz = 3200 Hz, you certainly don't need a high performance microcontroller, but it doesn't really hurt to use something that has a bit of RAM and enough power to do a bit of DSP on the signals, so I'd probably stick with an ARM design rather than going for an 8-bitter. All the more since the "high pin count" 8-bit MCUs tend to be not much cheaper than their 32 bit equivalents (with the analog circuitry and the package being the driving cost factor, core size and license costs don't really play much of a role). | |
| Jan 12, 2017 at 18:02 | comment | added | Marcus Müller | Oh! A 1000pcs order of MCP3208 costs $2.55 upwards. Definitely not cheaper to do that. | |
| Jan 12, 2017 at 18:00 | comment | added | Marcus Müller | I doubt it'll effectively lower the cost to reduce the level of integration. If the analog specs allow, I'd definitely prefer the MCU with integrated ADC from a complexity point of view. | |
| Jan 12, 2017 at 17:50 | comment | added | JFET Buffer | I also think it's a good idea for me to go with that design. Now that I think of it, the PSoC might not be needed after all. Although I could use 16ch on the built in ADC's, I'm thinking it might be better to just switch to a setup with 2x 8ch external ADC's (ex: MCP3208) to an AVR or MSP430 to lower the cost a bit. Do you agree/disagree with this idea? | |
| Jan 12, 2017 at 17:40 | vote | accept | JFET Buffer | ||
| Jan 12, 2017 at 17:27 | comment | added | Marcus Müller | Yes, do that, @JFETBuffer. Multi-Opamp-ICs and capacitor and resistor networks help making such designs halfway tolerable to build. | |
| Jan 12, 2017 at 17:26 | comment | added | Dave Tweed | @glen_geek: Yes, a delta-sigma converter implicitly includes a filter, and the same rules apply. | |
| Jan 12, 2017 at 16:44 | comment | added | JFET Buffer | Those are both excellent points, there. Would you say it would be best to just stick with the original idea of having the individual signal conditioning circuits fed into some multi-channel ADC? I was originally aiming to lower the component count when I design the PCB for this (hence the use of the PSoC), but I would definitely want choose the solution works the best for the overall design. | |
| Jan 12, 2017 at 16:28 | comment | added | glen_geek | Mux-ing a sigma-delta A-to-D requires a settling period too, although as you say, time for low-pass filter to settle would dominate. | |
| Jan 12, 2017 at 15:48 | history | answered | Dave Tweed | CC BY-SA 3.0 |