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Here's a link to my origional question at Stackoverflow.com Here's a link to my origional question at Stackoverflow.com

Here is the entire Module if that makes things more clear. I've only done a couple of simple Verilog projects before, so I'm sure my code is not great. But I did try to design it using a FSM. Maybe my problem is not what I thought. Thanks for you patience.

module AGC_controller ( input wire clk, reset, set_AGC, AMP_DO, output wire SDI, SCK, output reg inhibit_ADC, AMP_CS, //spi disable signals ** all disabled for =1 except AD_CONV. When AD_CONV=0, disabled. output wire DAC_CS, AD_CONV, SF_CEO, FPGA_INIT_B, output reg [7:0] led ); localparam [2:0] idle = 3'b000, set_up = 3'b001, start_data = 3'b010, wait_for_neg= 3'b011, wait_4 = 3'b100, next_bit = 3'b101; // wait_last = 3'b110; //signals //for SCK_clock reg SCK_gen, SCK_hold; integer i; reg en_SCK; wire neg_edge_SCK; initial begin SCK_gen = 0; i=0; end //SCK_generator always @(posedge clk) begin i <= i+1; SCK_hold <= SCK_gen; if(i == 10) begin SCK_gen <= ~SCK_gen; i <= 0; end end //detect neg edge of SCK assign neg_edge_SCK = SCK_hold & ~SCK_gen; //general signals reg [2:0] state_reg, state_next; integer bit_position; reg [7:0] AGC_buf; reg en_SDI; //FSM control always @(posedge clk, posedge reset) begin if (reset) state_reg <= idle; else state_reg <= state_next; end //FSM next state logic always @* begin state_next = state_reg; case(state_reg) idle: begin bit_position=7; AGC_buf = 8'b10011001; en_SCK = 1'b0; en_SDI = 1'b0; AMP_CS = 1'b1; inhibit_ADC = 1'b0; if(set_AGC) begin state_next = set_up; end end set_up: begin AMP_CS = 1'b0; inhibit_ADC = 1'b1; if ((SCK_gen) && (i < 9)) state_next = start_data; end start_data: begin en_SDI = 1'b1; if ((SCK_gen == 0) && (i==2)) begin state_next = wait_for_neg; en_SCK = 1'b1; end end wait_for_neg: begin if (neg_edge_SCK) begin state_next = wait_4; end end wait_4: begin if (i==4) begin //test code to light leds led[bit_position] = SDI; if (bit_position == 0) begin state_next = idle; end else begin state_next = next_bit; end end end next_bit: begin bit_position = bit_position - 1; state_next = wait_for_neg; end endcase end assign SDI = (en_SDI) ? AGC_buf[bit_position] : 1'bz; assign SCK = (en_SCK) ? SCK_gen : 1'bz; //spi disable signals ** all disabled for =1 except AD_CONV. When AD_CONV=0, disabled. assign DAC_CS = (state_reg != idle); assign AD_CONV = (state_reg == idle); assign SF_CEO = (state_reg != idle); assign FPGA_INIT_B = (state_reg != idle); endmodule 

Sorry. I couldn't upload the photos because i don't have a reputation score yet.

http://stackoverflowHere's a link to my origional question at Stackoverflow.com/q/9799641/1149741 

Here's a link to my origional question at Stackoverflow.com. It contains the photos.