Timeline for Detecting JTAG pinout
Current License: CC BY-SA 3.0
13 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Oct 28, 2017 at 23:12 | vote | accept | minto | ||
| Sep 1, 2017 at 11:35 | answer | added | Sean Houlihane | timeline score: 3 | |
| Aug 27, 2017 at 0:49 | history | edited | minto | CC BY-SA 3.0 | deleted 9 characters in body |
| Aug 24, 2017 at 18:41 | history | tweeted | twitter.com/StackElectronix/status/900790145569480704 | ||
| S Aug 24, 2017 at 15:40 | history | suggested | Daniel | CC BY-SA 3.0 | Corrected spelling and grammar, changed title. |
| Aug 24, 2017 at 15:26 | review | Suggested edits | |||
| S Aug 24, 2017 at 15:40 | |||||
| Aug 24, 2017 at 9:12 | answer | added | jpalanco | timeline score: 1 | |
| Aug 11, 2017 at 9:56 | history | edited | minto | CC BY-SA 3.0 | added 11 characters in body |
| Aug 11, 2017 at 9:33 | history | edited | minto | CC BY-SA 3.0 | added 11 characters in body |
| Aug 10, 2017 at 20:48 | history | edited | minto | CC BY-SA 3.0 | added 4 characters in body |
| Aug 10, 2017 at 20:02 | history | edited | minto | CC BY-SA 3.0 | deleted 328 characters in body |
| Aug 10, 2017 at 17:19 | comment | added | Peter Smith | The 4 signals being identified are the only mandatory pins. TRST (active low) is optional so some parts have it, others do not. Generally speaking, it is missing on FPGAs. | |
| Aug 10, 2017 at 14:17 | history | asked | minto | CC BY-SA 3.0 |