Timeline for What's the difference between setting SysTick Interrupt in NVIC and using it as an exception?
Current License: CC BY-SA 3.0
13 events
| when toggle format | what | by | license | comment | |
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| Sep 29, 2017 at 7:27 | comment | added | Jeroen3 | @PeterJ_01 If no priorities have been set, the number is the priority. Hence "base priority". | |
| Sep 29, 2017 at 7:17 | comment | added | 0___________ | IRQ number 6 not the priority 6, which makes a huge difference. Anyway the number is secondary. | |
| Sep 29, 2017 at 7:14 | history | edited | Jeroen3 | CC BY-SA 3.0 | deleted 2 characters in body |
| Sep 29, 2017 at 7:13 | comment | added | Jeroen3 | @PeterJ_01 It will still be IRQ 6. But you can change the priority groups in the NVIC. But it will always be 6, in every Cortex you get. | |
| Sep 29, 2017 at 7:12 | comment | added | Jeroen3 | @supercat Precisely, you can't. | |
| Sep 28, 2017 at 21:38 | comment | added | supercat | If the logic supplied by ARM feeds the clock signal to the systick counter as to other parts of the core (which I'm pretty sure it does), how could a chip manufacturer make systick non-synchronous? | |
| Sep 28, 2017 at 18:34 | comment | added | 0___________ | How the internal clock tree is designed is 100% up to chip manufacturer. It does not matter if there are any commercially available chips. Just this part of your answer is 100% wrong. Guaranteed might indeed not be the correct word - it is not the wrong word it is your wrong assumption that SysTick has constant priority. But it is the same as any other interrupt except HW exceptions which have the fixed priorities. IMO your answer is misleading and wrong and should be deleted. | |
| Sep 28, 2017 at 17:49 | comment | added | Jeroen3 | @PeterJ_01 Guaranteed might indeed not be the correct word. Do you know parts with a asynchronously clocked system tick? | |
| Sep 28, 2017 at 17:46 | history | edited | Jeroen3 | CC BY-SA 3.0 | guaranteed -> specified by ARM |
| Sep 28, 2017 at 17:00 | comment | added | 0___________ | @Jeroen3 The fundamental difference between the systick and peripheral interrupts is that the SysTick is guaranteed to be at priority 6 (0x003C) when it is available in the core. It is also part of the ARM Cortex, clocked by the same clock and thus synchronous. everything here is not the truth. It does not have any guaranteed priority and can be clocked by another clock source (if refeference clock is provided by the implementation) than the core clock. What is the source document of this revelations? | |
| Sep 28, 2017 at 14:10 | comment | added | Jeroen3 | @berendi That is correct. But they call every interrupt an exception since it is an exception to normal program flow. | |
| Sep 28, 2017 at 13:25 | comment | added | followed Monica to Codidact | Exception priorities are configurable on the Cortex-M series, except Reset, NMI and Hardfault. See the desciption of SCB->SHPR{1,2,3} in the programming manual. | |
| Sep 28, 2017 at 13:07 | history | answered | Jeroen3 | CC BY-SA 3.0 |