Timeline for How does an RS-latch work in the presence of propagation delays?
Current License: CC BY-SA 4.0
8 events
| when toggle format | what | by | license | comment | |
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| Jun 22, 2018 at 11:09 | comment | added | Ellen Spertus | @ElliotAlderson "Contamination delay" rings a bell and is something I can read more about. Thank you. | |
| Jun 22, 2018 at 10:46 | comment | added | Elliot Alderson | @supercat I have to agree with Ellen Spertus. I've been doing this for decades and never heard of "output disturb time". Sounds like the "contamination delay" from Harris texts. Data sheets commonly specify only maximum propagation delay for a gate. Flip-flops may provide a minimum time that data remains stable after the clock, but for logic gates we assume that the gate output starts changing as soon as the input changes. | |
| Jun 22, 2018 at 5:26 | comment | added | supercat | @EllenSpertus: Many data sheets aren't as detailed as they ideally should be. If an input and output edges are clean and have similar slope rates, propagation time and disturb time will be equal. Disturb time, however, is measured from the moment the input starts to switch to the time the output starts to switch, while propagation time is measured from when the input has fully switched to when the output has done so. | |
| Jun 21, 2018 at 22:25 | comment | added | Ellen Spertus | @supercat Thank you. This is the first I've heard of "output-disturb time". I don't recall ever seeing that on a datasheet (e.g., futurlec.com/74LS/74LS02.shtml, which just has Tphl and Tplh). | |
| Jun 21, 2018 at 22:15 | comment | added | supercat | @EllenSpertus: If one builds flip flop with two latches as its primary components, one will need a gate whose output-disturb time is guaranteed to be at least as long as the worst-case propagation time of some combinations of gates within the latches. It is not possible to build a flip flop entirely out of gates which do not specify a minimum delay between a disturbance on an input and a disturbance on the output | |
| Jun 21, 2018 at 19:32 | comment | added | Elliot Alderson | Flip-flops are built from latches, and if you violate the setup and/or hold time then the behavior is nondeterministic. This is called "metastability" and it can be big problem if you have asynchronous inputs to a synchronous system. Your intuition is spot on. | |
| Jun 21, 2018 at 18:45 | comment | added | Ellen Spertus | Thank you, but I was taught (and have taught) that edge-triggered flip-flops are built out of latches, so it seems that flip-flops would be nondeterministic if latches are. (I know I must be missing something.) | |
| Jun 21, 2018 at 18:32 | history | answered | Elliot Alderson | CC BY-SA 4.0 |