Timeline for Why is the dB of the FFT plots exceeding 96dB for these signals sampled by an 16 bit ADC
Current License: CC BY-SA 4.0
5 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Jul 21, 2018 at 17:01 | comment | added | Tony Stewart EE since 1975 | The 16 bit resolution is being wasted on 7.16Vdc +0.06/-0.10V to much fewer bits of dynamic range | |
| Jul 21, 2018 at 16:19 | answer | added | Tony Stewart EE since 1975 | timeline score: 0 | |
| Jul 21, 2018 at 16:18 | answer | added | Andy aka | timeline score: 1 | |
| Jul 21, 2018 at 15:34 | answer | added | Neil_UK | timeline score: 2 | |
| Jul 21, 2018 at 14:18 | history | asked | floppy380 | CC BY-SA 4.0 |