Timeline for Switch from JTAG to SWD with bitbang sequence on STM32F103VB
Current License: CC BY-SA 4.0
14 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Nov 7 at 3:19 | answer | added | woody | timeline score: 0 | |
| Apr 18 at 7:48 | comment | added | tepalia | GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable, ENABLE) should be used after switching to SWD. Use DBGMCU->CR to enable trace output (for SWO). | |
| Jan 29, 2024 at 14:32 | review | Close votes | |||
| Jan 29, 2024 at 16:38 | |||||
| Apr 16, 2020 at 16:26 | comment | added | HelpingHand | Hint 3: One option to circumvent your problem might be to reconfigure the JTDO=SWO/NTRST/JTDI pin (and the peer device) to a different protocol - SPI1 could be used unidirectionally (MISO-only). But this proposition requires 3 wires for communication instead of 1 - and it does not match your question... | |
| Apr 16, 2020 at 16:25 | comment | added | HelpingHand | Hint 2: I once encountered a JTAG-related erratum on an STM32F3 controller (I think that was STM32F302 or so). On your STM32F1, you might have a similar problem: Even if your research of spec documentation is correct, the µC might fail to implement it correctly. | |
| Apr 16, 2020 at 16:25 | comment | added | HelpingHand | Hint 1: ETM features (and the synchronous TPIU output it requires) are only present on those STM32 variants that include the GPIOE port group, so you should find it on your STM32F103VB (note the suffix characters!). As far as I can see from the ST documentation, ETM function blocks are not related to SWJ function blocks (apart from possible coupling to SWO configuration if both are present). I haven't dived much into the generic ARM documentation, though. | |
| Apr 8, 2019 at 5:35 | review | Close votes | |||
| Apr 13, 2019 at 3:05 | |||||
| S Apr 8, 2019 at 4:45 | history | suggested | Niteesh Shanbog | CC BY-SA 4.0 | Corrected grammar. |
| Apr 8, 2019 at 4:07 | review | Suggested edits | |||
| S Apr 8, 2019 at 4:45 | |||||
| Feb 11, 2019 at 16:59 | history | edited | Heneer | CC BY-SA 4.0 | Continued debugging with while(1){} in the OpenOCD code. |
| Jan 8, 2019 at 15:16 | history | edited | Heneer | CC BY-SA 4.0 | Continued debugging with changed OpenOCD code. |
| Jan 8, 2019 at 11:18 | comment | added | Sean Houlihane | Clock speed is irrelevant (so long as it is not too high). READID is part of the connection sequence, assuming you want to send any other SWD transaction. However, the SWO switching may only require the SWD-Select (but some of this switching may be impdef) | |
| Dec 21, 2018 at 18:00 | history | tweeted | twitter.com/StackElectronix/status/1076175561863630849 | ||
| Dec 21, 2018 at 11:21 | history | asked | Heneer | CC BY-SA 4.0 |