This is for stm32f401re First the DMA initialization

void init_spi1_dma(void) { DMA_InitTypeDef DMA_InitStructure; DMA_StructInit(&DMA_InitStructure); // // spi1 rx configuration // DMA_Cmd(DMA2_Stream0, DISABLE); while(DMA2_Stream0_BASE & 0x00000001); // wait for disable to take effect DMA_DeInit(DMA2_Stream0); DMA_InitStructure.DMA_Channel = DMA_Channel_3; DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; // receive // tell the DMA where to place the incoming characters // in this case only one char at a time // let the interrupt routine sort it out DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)dma_rx_buffer; DMA_InitStructure.DMA_BufferSize = (char)sizeof(dma_rx_buffer); DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&SPI1->DR; DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; DMA_InitStructure.DMA_Priority = DMA_Priority_High; DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull; DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; // // the interrupt flags for the DMA Stream: // DMA_IT: specifies the DMA interrupt pending bit to clear. // This parameter can be any combination of the following values: // DMA_IT_TCIFx: Streamx transfer complete interrupt // DMA_IT_HTIFx: Streamx half transfer complete interrupt // DMA_IT_TEIFx: Streamx transfer error interrupt // DMA_IT_DMEIFx: Streamx direct mode error interrupt // DMA_IT_FEIFx: Streamx FIFO error interrupt // Where x can be 0 to 7 to select the DMA Stream. DMA_ClearITPendingBit(DMA2_Stream0, DMA_IT_TCIF2 | DMA_IT_TEIF2 | DMA_IT_HTIF2 | DMA_IT_FEIF2 | DMA_IT_DMEIF2); DMA_Init(DMA2_Stream0, &DMA_InitStructure);

// Enable the SPI Rx DMA request SPI_DMACmd(SPI1, SPI_DMAReq_Rx, ENABLE);
// Enable DMA Stream Transfer Complete interrupt DMA_ITConfig(DMA2_Stream0, DMA_IT_TC | DMA_IT_TE | DMA_IT_DME, ENABLE);
// Enable the DMA Rx Stream DMA_Cmd(DMA2_Stream0, ENABLE);

}

now the interrupt // // dma spi interrupt // void init_spi_dma_nvic() { NVIC_InitTypeDef nvic_params;

//NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4); nvic_params.NVIC_IRQChannel = DMA2_Stream0_IRQn; nvic_params.NVIC_IRQChannelPreemptionPriority = 3; nvic_params.NVIC_IRQChannelSubPriority = 0; nvic_params.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&nvic_params); }

// // spi1 rx dma interrupt // void DMA2_Stream0_IRQHandler(void) { static uint16_t i = 0;

if(rcvd == 0) i = 0;

rcvd++; /* Test on DMA Stream Transfer Complete interrupt */ if (DMA_GetITStatus(DMA2_Stream0, DMA_IT_TCIF0)) { // place the incoming char away rx_buffer[i++] = dma_rx_buffer[0]; // Clear DMA Stream Transfer Complete interrupt pending bit DMA_ClearITPendingBit(DMA2_Stream0, DMA_IT_TCIF0);

} }

This is for stm32f401re 
First the DMA initialization

void init_spi1_dma(void) { DMA_InitTypeDef DMA_InitStructure; DMA_StructInit(&DMA_InitStructure); // // spi1 rx configuration // DMA_Cmd(DMA2_Stream0, DISABLE); while(DMA2_Stream0_BASE & 0x00000001); // wait for disable to take effect DMA_DeInit(DMA2_Stream0); DMA_InitStructure.DMA_Channel = DMA_Channel_3; DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; // receive // tell the DMA where to place the incoming characters // in this case only one char at a time // let the interrupt routine sort it out DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)dma_rx_buffer; DMA_InitStructure.DMA_BufferSize = (char)sizeof(dma_rx_buffer); DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&SPI1->DR; DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; DMA_InitStructure.DMA_Priority = DMA_Priority_High; DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull; DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; // // the interrupt flags for the DMA Stream: // DMA_IT: specifies the DMA interrupt pending bit to clear. // This parameter can be any combination of the following values: // DMA_IT_TCIFx: Streamx transfer complete interrupt // DMA_IT_HTIFx: Streamx half transfer complete interrupt // DMA_IT_TEIFx: Streamx transfer error interrupt // DMA_IT_DMEIFx: Streamx direct mode error interrupt // DMA_IT_FEIFx: Streamx FIFO error interrupt // Where x can be 0 to 7 to select the DMA Stream. DMA_ClearITPendingBit(DMA2_Stream0, DMA_IT_TCIF2 | DMA_IT_TEIF2 | DMA_IT_HTIF2 | DMA_IT_FEIF2 | DMA_IT_DMEIF2); DMA_Init(DMA2_Stream0, &DMA_InitStructure); // Enable the SPI Rx DMA request SPI_DMACmd(SPI1, SPI_DMAReq_Rx, ENABLE); // Enable DMA Stream Transfer Complete interrupt DMA_ITConfig(DMA2_Stream0, DMA_IT_TC | DMA_IT_TE | DMA_IT_DME, ENABLE); // Enable the DMA Rx Stream DMA_Cmd(DMA2_Stream0, ENABLE); } 

now the interrupt

// // dma spi interrupt // void init_spi_dma_nvic() { NVIC_InitTypeDef nvic_params; //NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4); nvic_params.NVIC_IRQChannel = DMA2_Stream0_IRQn; nvic_params.NVIC_IRQChannelPreemptionPriority = 3; nvic_params.NVIC_IRQChannelSubPriority = 0; nvic_params.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&nvic_params); } // // spi1 rx dma interrupt // void DMA2_Stream0_IRQHandler(void) { static uint16_t i = 0; if(rcvd == 0) i = 0; rcvd++; /* Test on DMA Stream Transfer Complete interrupt */ if (DMA_GetITStatus(DMA2_Stream0, DMA_IT_TCIF0)) { // place the incoming char away rx_buffer[i++] = dma_rx_buffer[0]; // Clear DMA Stream Transfer Complete interrupt pending bit DMA_ClearITPendingBit(DMA2_Stream0, DMA_IT_TCIF0); } }