Timeline for PCIe Gen2 PLL lock issue
Current License: CC BY-SA 4.0
11 events
| when toggle format | what | by | license | comment | |
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| May 24, 2020 at 4:06 | history | bumped | CommunityBot | This question has answers that may be good or bad; the system has marked it active so that they can be reviewed. | |
| Jan 21, 2020 at 11:01 | history | bumped | CommunityBot | This question has answers that may be good or bad; the system has marked it active so that they can be reviewed. | |
| Sep 19, 2019 at 8:01 | history | bumped | CommunityBot | This question has answers that may be good or bad; the system has marked it active so that they can be reviewed. | |
| Feb 24, 2019 at 23:17 | comment | added | analogsystemsrf | @ Marcus If the bit rate is 1,500MHz and the loop bandwidth is 1.5Mhz, then that 3pS gets accumulated and becomes 3pS * sqrt(1,000) = 100 picoSeconds. | |
| Feb 24, 2019 at 21:15 | comment | added | Captain Barnacles | When I read your post you have need to have a few goes locking the PHY PLL to the clock. Then you power it off and back on and it's again unlocked. So do you need to repeat your process ? Have you got a 100MHz signal generator you can connect into the PHY ? To rule out the PC. The datasheet may also have a sequence for the PLL getting lock. | |
| Feb 24, 2019 at 21:03 | answer | added | analogsystemsrf | timeline score: 1 | |
| Feb 24, 2019 at 20:28 | comment | added | Marcus Müller | I'll have to agree with you – after having read the spec (PCIe Base Specification Revision 2.1, section 4.3.3.1) as referred to in that whitepaper (always read the original sources if possible!), they specify a frequency range-specific RMS jitter which makes me sigh a little, but OK. So, what they mean is that your phase noise needs low enough that if you, in the end, consider the filtered jitter, the RMS (which is essentially the standard deviation of that stochastic entity) is below 3 ps. 3 ps RMS jitter just doesn't make too much sense for a < 1.5 MHz signal... | |
| Feb 24, 2019 at 19:49 | comment | added | Amit | @ Marcus : microsemi.com/document-portal/doc_view/… on page 5 bottom | |
| Feb 24, 2019 at 19:41 | comment | added | Marcus Müller | Hm, no, that's not how jitter works: I think you might be simply misreading the specs. Can you refer us to where you're reading these "10 kHz to 1.5 MHz"? | |
| Feb 24, 2019 at 19:39 | history | edited | Marcus Müller | CC BY-SA 4.0 | deleted 184 characters in body |
| Feb 24, 2019 at 19:17 | history | asked | Amit | CC BY-SA 4.0 |