Timeline for Design a high accuracy ADC circuit (example of differential ADC LTC2348 for PSD signals)
Current License: CC BY-SA 4.0
3 events
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| Sep 8, 2020 at 21:35 | comment | added | user42875 | Thank you very much for your answer. I thought no one would answer my question so I went away, but I've read somewhere you should have gotten half of the reward in spite of the fact the bounty expired before I saw your answer. I do have 2 questions: a) why do you recommend to isolate the ADC digital lines from the uC lines when the currents can't loop through the supplies (they are isolated from mains)? and b) How do you "keep this zone free of return currents"? Should I NOT use a ground plane and route the GND far from the signals? Wouldn't that increase the parasitic loop inductance? | |
| Sep 8, 2020 at 21:25 | vote | accept | user42875 | ||
| Aug 25, 2020 at 18:11 | history | answered | Voltage Spike♦ | CC BY-SA 4.0 |