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Your classmate is wrongly treating the transistors in your circuit as magical devices whose behaviour is completely controlled by something that appears at the gate and only the gate. They are failing to see the transistor in your digital logic circuit as an actual transistor.

MOSFETs don't react to ones and zeroes at the gate. They don't react to the voltage at the gate either (this actually doesn't make sense since the gate is just one pin but a voltage is always a difference between two points). The MOSFET cannot and does not care about the voltage at any one pin. It only cares about the voltage between two pins, and what controls a MOSFET is the voltage difference between its gate and source pin.

That means you can't have PMOS on the low-side and NMOS on the high-side if you are driving the gate with a voltage referenced to ground. The NMOS must go on the low-side and the PMOS must go on the high-side so that their source pins are connected to a fixed voltage if you plan to drive their gates with a voltage that is referenced to a fixed voltage (i.e. ground).

If the source pin on an NMOS is not connected to a fixed potential, but you are drive the gate with a voltage referenced to ground, it becomes a source follower and does not behave like a digital switch. Something similar happens with a PMOS if you do not connect its source pin to a fixed rail and drive the gate relative to a fixed voltage.

That means with 4 transistors, it will always be a NAND, and you need the two-transistor inverter to turn it into an AND.

It is the same reason an inverter is a PMOS on top and an NMOS on the bottom, and you can't make a non-inverting buffer by just putting the NMOS on top and a PMOS on the bottom.

If you want to work out yourself with circuit analysis or whatnot for why it won't work, don't bother trying to do it with a NAND gate. Instead, do it for the non-inverting buffer with a NMOS on top and PMOS on the bottom. That will be sufficient for you to understand. You could even do it with a PMOS on the bottom and a pull-up resistor on top, or an NMOS on the top and a pull-down resistor on the bottom. Then note how your source voltage changes in the circuit as you try to turn transistors on and off, and remember that the gate-source voltage is what is controlling the MOSFET.

Your classmate is wrongly treating the transistors in your circuit as magical devices whose behaviour is completely controlled by something that appears at the gate and only the gate. They are failing to see the transistor in your digital logic circuit as an actual transistor.

MOSFETs don't react to ones and zeroes at the gate. They don't react to the voltage at the gate either (this actually doesn't make sense since the gate is just one pin but a voltage is always a difference between two points). The MOSFET cannot and does not care about the voltage at any one pin. It only cares about the voltage between two pins, and what controls a MOSFET is the voltage difference between its gate and source pin.

That means you can't have PMOS on the low-side and NMOS on the high-side if you are driving the gate with a voltage referenced to ground. The NMOS must go on the low-side and the PMOS must go on the high-side so that their source pins are connected to a fixed voltage if you plan to drive their gates with a voltage that is referenced to a fixed voltage (i.e. ground).

If the source pin on an NMOS is not connected to a fixed potential, but you drive the gate with a voltage referenced to ground, it becomes a source follower and does not behave like a digital switch. Something similar happens with a PMOS if you do not connect its source pin to a fixed rail and drive the gate relative to a fixed voltage.

That means with 4 transistors, it will always be a NAND (or NOR), and you need the two-transistor inverter to turn it into an AND (or OR).

It is the same reason an inverter is a PMOS on top and an NMOS on the bottom, and you can't make a non-inverting buffer by just putting the NMOS on top and a PMOS on the bottom; you need at least four transistors (two inverters) for that behaviour.

If you want to work out yourself with circuit analysis or whatnot for why it won't work, don't bother trying to do it with a NAND gate. Instead, do it for the non-inverting buffer with a NMOS on top and PMOS on the bottom. That will be sufficient for you to understand. You could even do it with a PMOS on the bottom and a pull-up resistor on top, or an NMOS on the top and a pull-down resistor on the bottom. Then note how your source voltage changes in the circuit as you try to turn transistors on and off, and remember that the gate-source voltage is what is controlling the MOSFET.

Your classmate is wrongly treating the transistors in your circuit as magical devices whose behaviour is completely controlled by something that appears at the gate and only the gate. They are failing to see the transistor in your digital logic circuit as an actual transistor.

MOSFETs don't react to ones and zeroes at the gate. They don't react to the voltage at the gate either (this actually doesn't make sense since the gate is just one pin but a voltage is always a difference between two points). The MOSFET cannot and does not care about the voltage at any one pin. It only cares about the voltage between two pins, and what controls a MOSFET is the voltage difference between its gate and source pin.

That means you can't have PMOS on the low-side and NMOS on the high-side if you are driving the gate with a voltage referenced to ground. The NMOS must go on the low-side and the PMOS must go on the high-side so that their source pins are connected to a fixed voltage if you plan to drive their gates with a voltage that is referenced to a fixed voltage (i.e. ground).

If the source pin on an NMOS is not connected to a fixed potential, but you are drive the gate with a voltage referenced to ground, it becomes a source follower and does not behave like a digital switch. Something similar happens with a PMOS if you do not connect its source pin to a fixed rail and drive the gate relative to a fixed voltage.

That means with 4 transistors, it will always be a NAND, and you need the two-transistor inverter to turn it into an AND.

It is the same reason an inverter is a PMOS on top and an NMOS on the bottom, and you can't make a non-inverting buffer by just putting the NMOS on top and a PMOS on the bottom.

Your classmate is wrongly treating the transistors in your circuit as magical devices whose behaviour is completely controlled by something that appears at the gate and only the gate. They are failing to see the transistor in your digital logic circuit as an actual transistor.

MOSFETs don't react to ones and zeroes at the gate. They don't react to the voltage at the gate either (this actually doesn't make sense since the gate is just one pin but a voltage is always a difference between two points). The MOSFET cannot and does not care about the voltage at any one pin. It only cares about the voltage between two pins, and what controls a MOSFET is the voltage difference between its gate and source pin.

That means you can't have PMOS on the low-side and NMOS on the high-side if you are driving the gate with a voltage referenced to ground. The NMOS must go on the low-side and the PMOS must go on the high-side so that their source pins are connected to a fixed voltage if you plan to drive their gates with a voltage that is referenced to a fixed voltage (i.e. ground).

If the source pin on an NMOS is not connected to a fixed potential, but you are drive the gate with a voltage referenced to ground, it becomes a source follower and does not behave like a digital switch. Something similar happens with a PMOS if you do not connect its source pin to a fixed rail and drive the gate relative to a fixed voltage.

That means with 4 transistors, it will always be a NAND, and you need the two-transistor inverter to turn it into an AND.

It is the same reason an inverter is a PMOS on top and an NMOS on the bottom, and you can't make a non-inverting buffer by just putting the NMOS on top and a PMOS on the bottom.

If you want to work out yourself with circuit analysis or whatnot for why it won't work, don't bother trying to do it with a NAND gate. Instead, do it for the non-inverting buffer with a NMOS on top and PMOS on the bottom. That will be sufficient for you to understand. You could even do it with a PMOS on the bottom and a pull-up resistor on top, or an NMOS on the top and a pull-down resistor on the bottom. Then note how your source voltage changes in the circuit as you try to turn transistors on and off, and remember that the gate-source voltage is what is controlling the MOSFET.

Your classmate is wrongly treating the transistors in your circuit as magical devices that only reacts to something that appears solely at the gate. They are failing to see the transistor in your digital logic circuit as an actual transistor.

MOSFETs don't react to ones and zeroes at the gate. They don't react to the voltage at the gate either (this actually doesn't make sense since the gate is just one pin but a voltage is always a difference between two points). The MOSFET cannot and does not care about the voltage at any one pin. It only cares about the voltage between two pins, and what controls a MOSFET is the voltage difference between its gate and source pin.

That means you can't have PMOS on the low-side and NMOS on the high-side if you are driving the gate with a voltage referenced to ground. The NMOS must go on the low-side and the PMOS must go on the high-side.

If the source pin on an NMOS is not connected to a fixed potential, but you are drive the gate with a voltage referenced to ground, it becomes a source follower and does not behave like a digital switch. Something similar happens with a PMOS if you do not connect its source pin to a fixed rail and drive the gate relative to a fixed voltage.

That means with 4 transistors, it will always be a NAND, and you need the two-transistor inverter to turn it into an AND.

It is the same reason an inverter is a PMOS on top and an NMOS on the bottom, and you can't make a non-inverting buffer by just putting the NMOS on top and a PMOS on the bottom.

Your classmate is wrongly treating the transistors in your circuit as magical devices whose behaviour is completely controlled by something that appears at the gate and only the gate. They are failing to see the transistor in your digital logic circuit as an actual transistor.

MOSFETs don't react to ones and zeroes at the gate. They don't react to the voltage at the gate either (this actually doesn't make sense since the gate is just one pin but a voltage is always a difference between two points). The MOSFET cannot and does not care about the voltage at any one pin. It only cares about the voltage between two pins, and what controls a MOSFET is the voltage difference between its gate and source pin.

That means you can't have PMOS on the low-side and NMOS on the high-side if you are driving the gate with a voltage referenced to ground. The NMOS must go on the low-side and the PMOS must go on the high-side so that their source pins are connected to a fixed voltage if you plan to drive their gates with a voltage that is referenced to a fixed voltage (i.e. ground).

If the source pin on an NMOS is not connected to a fixed potential, but you are drive the gate with a voltage referenced to ground, it becomes a source follower and does not behave like a digital switch. Something similar happens with a PMOS if you do not connect its source pin to a fixed rail and drive the gate relative to a fixed voltage.

That means with 4 transistors, it will always be a NAND, and you need the two-transistor inverter to turn it into an AND.

It is the same reason an inverter is a PMOS on top and an NMOS on the bottom, and you can't make a non-inverting buffer by just putting the NMOS on top and a PMOS on the bottom.