What you are describing is a direct memory access (DMA) operation.

It looks like the Teensy 4.1 uses an NXP MIMXRT1062 processor, and that processor does have a DMA engine -- but in order to work for you that DMA engine would have to work with parallel data in, and would have to be otherwise compatible with the ADC you're proposing to use. Unless there's something already in the Teensy ecosystem that supports it, you're going to have a long uphill battle to make it work.

To put the above statement into perspective: I've been doing this stuff for 30 years now; if my boss came into my cubicle right now (oh, COVID, when will you be done?) and asked me how long it would take I'd say "I've just spent 60 seconds skimming the datasheet, and the chip has DMA -- at minimum, a month; at maximum, maybe never.

So -- dig in to the datasheet, find a Teensy forum to ask your question, and start learning a lot.

If you can't do this using the processor's DMA, then your best bet if you want to use the Teensy is to use a CPLD from Lattice or Xilinx or whoever plus an external RAM chip that handles the DMA for you, and lets you access the memory from the Teensy. This will be an even longer steeper uphill battle.

If you can't use the processor's DMA and you're willing to give up on using the Teensy, then your best bet overall may be to get dev board for an FPGA with an embedded processor (like Xilinx's Zynq), and do it all there. If I'm correct about your abilities this will be your longest and steepest uphill battle, but when you're done you'll have a board with an ADC mezzanine board (or even built in -- some of the Zynq dev boards come with ADCs) instead of a Teensy with all sorts of crap glommed onto it.

What you are describing is a direct memory access (DMA) operation.

It looks like the Teensy 4.1 uses an NXP MIMXRT1062 processor, and that processor does have a DMA engine -- but in order to work for you that DMA engine would have to work with parallel data in, and would have to be otherwise compatible with the ADC you're proposing to use. Unless there's something already in the Teensy ecosystem that supports it, you're going to have a long uphill battle to make it work.

(n.b: See Dave Tweed's answer pertaining to the CMOS Sensor Interface -- if you can make that work it should have more than enough speed.)

To put the above statement into perspective: I've been doing this stuff for 30 years now; if my boss came into my cubicle right now (oh, COVID, when will you be done?) and asked me how long it would take I'd say "I've just spent 60 seconds skimming the datasheet, and the chip has DMA -- at minimum, a month; at maximum, maybe never.

So -- dig in to the datasheet, find a Teensy forum to ask your question, and start learning a lot.

If you can't do this using the processor's DMA, then your best bet if you want to use the Teensy is to use a CPLD from Lattice or Xilinx or whoever plus an external RAM chip that handles the DMA for you, and lets you access the memory from the Teensy. This will be an even longer steeper uphill battle.

If you can't use the processor's DMA and you're willing to give up on using the Teensy, then your best bet overall may be to get dev board for an FPGA with an embedded processor (like Xilinx's Zynq), and do it all there. If I'm correct about your abilities this will be your longest and steepest uphill battle, but when you're done you'll have a board with an ADC mezzanine board (or even built in -- some of the Zynq dev boards come with ADCs) instead of a Teensy with all sorts of crap glommed onto it.