Timeline for SPI clock signal (SCLK) usage in FPGA SPI slave

4 events

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Mar 19, 2021 at 14:01	comment	added	Dave Tweed		@quantum231: A clock domain is a clock domain, no matter how big it is. You always need to deal with it and its CDCs properly. Sure, sometimes you can use strictly local routing resources, and sometimes it's just as convenient to use a global resource. But that's just an implementation detail.
Mar 19, 2021 at 13:00	comment	added	Simon Richter		@quantum231, you have multiple clock distribution networks everywhere, otherwise the compiler would be very constrained when trying to lay out clock domain crossing logic -- so the SPI clock will be available to a large segment of the FPGA, but there is no requirement to use it. CPLDs are much more restricted there, and this would definitely be a concern here.
Mar 19, 2021 at 12:56	comment	added	quantum231		Dave the SCLK feeds only a few registers inside the whole design. When we say "clock domain" it makes it sound like the SCLK will feed into one of the clock input pins and the be distributed across a portion of the FPGA as its sole clock signal. This implies that the whole portion of the FPGA (maybe a quarter that uses this clock routing) will be unuseable to to being locked into a single SPI clock domain.
Mar 19, 2021 at 11:40	history	answered	Dave Tweed	CC BY-SA 4.0