Timeline for Why are open-drain outputs needed?
Current License: CC BY-SA 4.0
10 events
| when toggle format | what | by | license | comment | |
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| Jul 12, 2021 at 18:06 | vote | accept | anmomu92 | ||
| Apr 8, 2021 at 14:50 | comment | added | The Photon | @Alnitak, I think it was more common to think about active low logic back in the days of large circuits with many discrete logic chips, when you'd switch back and forth between active low and active high to minimize the number of chips needed. But still if you want to always think about the logic in terms of voltage levels, then you need to remember you're considering everything as active high logic. (And then OP's answer, which calls the logic "wired OR", still needs a comment to say it's actually "wired AND" for your way of thinking about it) | |
| Apr 8, 2021 at 13:28 | comment | added | Alnitak | See also for example this 74LS138 data sheet where G2A and G2B are both active low inputs, and both must be active to enable the chip. The datasheet uses G2 = G2A + G2B (an OR) because it needs L = L + L. :shrug: Either way, if I'm replacing a bunch of ~IRQ outputs that are wired-FOO with discrete logic, it's an AND gate I need, not an OR gate. | |
| Apr 8, 2021 at 13:15 | comment | added | Alnitak | @ThePhoton That's the answer I expected, except that logic chip truth tables aren't written with 1's or 0's, they're written with L or H. If you treat the network of inputs and outputs as a black box that doesn't "know" whether it's being used in an active-high or an active-low configuration it makes more sense IMHO to reference the voltage levels, not the logic levels. | |
| Apr 8, 2021 at 6:42 | comment | added | slebetman | @Alnitak asserted (goes low) if any of the inputs go low - That's the definition of OR. The definition of AND is the IRQ is asserted only when all inputs go low | |
| Apr 7, 2021 at 15:07 | comment | added | The Photon | @Alnitak, if they're active-low inputs, then a low voltage is a logic '1'. So if any of the inputs going to a low voltage produces a low level, that's an OR function, not AND. | |
| Apr 7, 2021 at 11:28 | comment | added | Alnitak | @ThePhoton why that way around? If I have multiple active-low IRQ inputs all wired together, the net result is that the line is asserted (goes low) if any of the inputs go low. With reference to the voltage levels, that looks like an AND gate, not an OR gate. | |
| Apr 7, 2021 at 6:31 | comment | added | Genorme | A good practical example of this is the I2C bus. | |
| Apr 7, 2021 at 0:28 | comment | added | The Photon | It's wired-or in active-low logic and wired-and in active high logic. | |
| Apr 6, 2021 at 15:52 | history | answered | BB ON | CC BY-SA 4.0 |