Timeline for FPGA pins driven high at power-up ‒ what can I do to get around this?
Current License: CC BY-SA 4.0
10 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Nov 8, 2021 at 16:31 | vote | accept | Cal-linux | ||
| Nov 5, 2021 at 16:12 | answer | added | icodeplenty | timeline score: 2 | |
| Nov 5, 2021 at 13:29 | comment | added | Cal-linux | @Kartman ‒ I will try your suggestion. However, the pins ultimately need to be outputs. I want to light the LED with a PWM type of signal, to do have a "dimmer" effect. So, my top module has: assign led_g1 = (counter[16:10] < intensity);, where intensity is set to all-zeros by a (synchronous) reset signal, and led_g1 is defined as output wire led_g1;. Sounds like this could be the cause (after the logic starts, this intensity or counter registers may have weird values?) What could be an approach to tackle this issue? Configure the output as tri-state? | |
| Nov 5, 2021 at 13:25 | comment | added | jonk | @Cal-linux Do you see that oversight now as a mistake? Can that be used during configuration, and perhaps just a little longer -- long enough for internal equilibrium to complete, to solve the current problem? If so, then there was a mechanism available. It just wasn't used. Is that about the summary of it? (Aside from the fact that there's no doc on I/O pin state during configuration.) | |
| Nov 5, 2021 at 13:16 | comment | added | Cal-linux | @jonk ‒ The datasheet explicitly state that all IO pins are maintained at high-impedance until the power supply voltage is high enough to guarantee reliable operation. However, that says nothing about configuration (loading LUTs from internal flash, etc.). I see nothing about that. There is one pin, TOE (OE for Output Enable) that can be used to disable all IO pins (i.e., set them to high-impedance), but I never considered making use of TOE, so I just hard-wired a pull-up resistor to VCCCORE. | |
| Nov 5, 2021 at 6:51 | comment | added | Lorenzo Marcantonio | I don't know Lattice but there is some often some flag at the start of configuration bitstream that say how to handle unused IOs (some part can use these as extra grounds for example). But before the start of load you can't really do anything, the real fix is to the hardware. | |
| Nov 5, 2021 at 5:20 | comment | added | Mitu Raj | Usually power up sequencing sends IOs of FPGA to high impedance. | |
| Nov 5, 2021 at 1:03 | comment | added | Kartman | At what stage are the outputs going high? Power up, during config or when your logic is running? Load up a bitstream that has the pins uncommitted or as inputs. See what happens. If there!s no flash, then that suggests it might be your logic. | |
| Nov 5, 2021 at 1:00 | comment | added | jonk | I've not used them, but isn't there a specification in the datasheet with respect to holding the I/O pin driver circuitry in a high impedance state during POR and then during initial boot/configuration of the device? I don't want to take the time to haul through them myself. But is that kind of information missing? (I was of course tempted to just say, when using Lattice just ground all the pins to be safe. But of course I then decided not to write any of that. ;) | |
| Nov 5, 2021 at 0:38 | history | asked | Cal-linux | CC BY-SA 4.0 |