Timeline for Need help shrinking a 4-bit binary Adder/Subtractor/Multiplier calculator circuit
Current License: CC BY-SA 4.0
42 events
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| Nov 8, 2021 at 6:23 | answer | added | jonk | timeline score: -1 | |
| Nov 7, 2021 at 9:08 | comment | added | jonk | @CarlJeffersonLay Best wishes. It took me quite a while to design and build my first 8-bit CPU, finished in late 1974, early 1975. After that, stuff like this got kind of easy to do, I guess. Lots of suffering. But worth the results in that day! | |
| Nov 7, 2021 at 8:35 | comment | added | Carl Jefferson Lay | @jonk Thank you very much! I also arrived at your first simplified Binary-BCD, seeing that the ground makes a lot of the gates always output 0, but didn't know you can simplify it further by observing patterns like 101 automatically means 8 in the 7-segment! I will try to do the binary to BCD myself. I am still studying the circuit you made, but I reckon my current design should be way below 70 ICs. Thanks! | |
| Nov 7, 2021 at 6:04 | comment | added | jonk | @CarlJeffersonLay Sorry. Not 7400, but 7408. Memory fades. | |
| Nov 7, 2021 at 2:31 | comment | added | jonk | @CarlJeffersonLay That's only 49 IC packages. (2) 7406, (19) 7400, (11) 7432, (3) 7402, and (14) 7486. | |
| Nov 7, 2021 at 2:11 | comment | added | jonk | @CarlJeffersonLay After dinner a couple of other changes came to mind. Here is a 191 gate version. | |
| Nov 6, 2021 at 23:38 | comment | added | jonk | @CarlJeffersonLay I get a total of 203 gates: 10 inverters, 79 AND, 49 OR, 10 NOR, and 55 XOR. If I were doing this with 7400 series parts I might look at shuffling these around a bit to get the package count down. But that works good. And there is still one remaining obvious thing to do in order to reduce it further, as I'm using a full 7-bit binary to BCD conversion. It's likely a gate or two can be removed as there isn't a need for all of the 7-bit range. | |
| Nov 6, 2021 at 11:14 | comment | added | Russell McMahon♦ | Carl: [[Edited 9+9=18. Advise if not what was intended RM]] | |
| Nov 6, 2021 at 9:59 | comment | added | Carl Jefferson Lay | @jonk Thank you very much! I saw your binary to 7 segment example for 4-bit inputs, did you begin your design with a truth table? I can imagine how to make the truth table for a 4-bit input for a 7 segment, but I am not too sure if the same process can be applied to a 7-bit input for two 7-segments. I also considered using hexadecimal to 7 segment decoder instead, but that would mean using arithmetic circuits to compensate the numbers 10-15. | |
| Nov 6, 2021 at 9:26 | comment | added | the busybee | Instead of a sea of logic ICs you might like to look at a CPLD or a small FPGA. But this adds a complete new set of challenges. The "program" could be made out of simple gates, though. -- Any idea with sequential processes needs some kind of a clock, which I don't see here. Self-clocked circuits have their very own problems. | |
| Nov 6, 2021 at 8:04 | comment | added | jonk | @CarlJeffersonLay I'll +1 your question. You are working the issue! | |
| Nov 6, 2021 at 7:48 | comment | added | jonk | @CarlJeffersonLay Here. That should get you to 45. There's probably more to be found and removed. 4 AND gates in each of the 4-bit terms on the left (16 total) and then 5 XORs and then 2 half-adders with 2 gates each and then 4 full adders with 5 gates each. You'll benefit a LOT by bypassing the binary to BCD and then BCD to 7-seg process and going, instead, directly from your binary outputs to the 7-seg display drive. | |
| Nov 6, 2021 at 7:42 | comment | added | Carl Jefferson Lay | @jonk Thanks! Found 2 so far, searching for more. | |
| Nov 6, 2021 at 6:46 | comment | added | jonk | @CarlJeffersonLay You need to observe which bits are never '1' to reduce to 45. It's not difficult. | |
| Nov 6, 2021 at 5:32 | history | edited | Carl Jefferson Lay | CC BY-SA 4.0 | added 26 characters in body |
| Nov 6, 2021 at 5:26 | history | edited | Carl Jefferson Lay | CC BY-SA 4.0 | added 26 characters in body |
| Nov 6, 2021 at 5:25 | comment | added | Carl Jefferson Lay | @jonk Yes, my inputs are only BCD 0-9 values. And yes, I want to include the minus sign in my output, and my circuit already has an output for that minus sign, so it is not a problem. I shrunk the 2's complement circuit like you said, updated in the picture. Currently working on the multiplier, but I always end up with more than 50 gates when I follow Wallace multplication. | |
| Nov 5, 2021 at 23:35 | comment | added | jonk | @CarlJeffersonLay You should be able to implement the BCD times BCD multiplier (binary output) with 45 2-input gates, worst case from beginning to end. I think that can be reduced by a few more gates. But that's the low-hanging fruit result I get. | |
| Nov 5, 2021 at 21:49 | comment | added | jonk | @CarlJeffersonLay Of course, you probably don't need all that because the ONLY way you get any negative values is from your subtractor. By definition, your multiplication can only generate positive values. | |
| Nov 5, 2021 at 21:43 | comment | added | jonk | @CarlJeffersonLay For example, here's how I'd perform the absolute value function. | |
| Nov 5, 2021 at 21:34 | comment | added | jonk | @CarlJeffersonLay I did all of this for an 8-bit CPU using 7400 parts. But I used the 7483! I didn't have any limitations set by others. I just wanted to learn and make something. I'd like to clarify a few details. Are your input values only BCD (0-9) values? And, if you perform 4 - 7 = -3, do you want a minus sign and "-03" as your output? Or do you just want "03" as your output without any sign indication? For absolute value with sign output (7-bit) you only need 4 OR gates, 5 AND gates, and 5 XOR gates total. That works with both + and - binary and outputs correctly. | |
| Nov 5, 2021 at 20:05 | comment | added | Carl Jefferson Lay | @jonk My limitation is I am only allowed to use AND, OR, XNOR, XOR, and NOT gates. No decoder, adder, or other types of ICs allowed. There isn't any limitation on open collector outputs, but those ICs (with the exception of 74266) are incredibly rare in our area, so I would preferably use the common, totem-pole outputs. | |
| Nov 5, 2021 at 20:05 | comment | added | Carl Jefferson Lay | @jonk I'll try first shrinking the multiplier, as per your advice. I think I saw some circuits that are similar to what you described. Also, yes I am taking the absolute value of the negative outputs of the add/sub ALU. I noticed that the negative differences are being outputted in 2's complement, so I designed a 2's complement circuit to get the absolute value, and also the "negative sign" from the inverted output of the carry of the left-most full adder. I'll try to redesign it with fewer gates. | |
| Nov 5, 2021 at 20:05 | comment | added | Carl Jefferson Lay | @jonk Thanks for the suggestion on the binary to 7-seg! I'll study that example for a while. I'm not too sure what you mean by 4x4=8, 4+4 =5, and 4-4=5. But my inputs are limited to 1 digit positive integers (decimal), 0-9. Therefore the maximum of addition is 9+9 = 18, the minimum of subtraction is 0-9 = -9, and the maximum of my multiplication is 9x9 = 81. Since 81 is a 7-bit binary number, based from your example, I would need to design something that employs the same procedure, but for 7-bit inputs? [[Edited 9+9=18. Advise if not what was intended RM]] | |
| Nov 5, 2021 at 19:04 | comment | added | jonk | @CarlJeffersonLay And finally, are you allowed to use open collector output logic? That would allow wire-OR, which can reduce the number of gates still further. | |
| Nov 5, 2021 at 19:00 | review | Close votes | |||
| Nov 10, 2021 at 3:08 | |||||
| Nov 5, 2021 at 18:57 | comment | added | jonk | @CarlJeffersonLay Also, 4x4 to 8 bits only requires 48 gates total, including all those initial AND gates used for each multiplication term. Also consider using a Wallace tree multiplier. Same number of gates. Less delay, though. And are you taking the absolute value (or 'signed magnitude') of your add/sub ALU for negative values??? That can also be done with fewer gates, I believe, than what I see there. | |
| Nov 5, 2021 at 18:04 | comment | added | jonk | @CarlJeffersonLay I also take it that you are not allowed to use the 7483 or similar, correct? What about the 74154 kind of device? Etc? What are your full limitations and allowances? | |
| Nov 5, 2021 at 18:02 | comment | added | jonk | @CarlJeffersonLay One thing you could consider immediately is doing the binary to 7-seg, directly, and not go through a binary to BCD step only to be followed by a BCD to 7-seg set of logic. You can combine the two. It will take some thought, though. But it will reduce the logic required. Here's an example of something that counts the number of '1's in a 4-bit value and directly drives a 7-seg display to show the count, for example. Do I gather correctly that you must provide 4x4=8 multiplication along with 4+4=5 addition and 4-4=5 subtraction (sign?) | |
| Nov 5, 2021 at 17:48 | history | edited | Carl Jefferson Lay | CC BY-SA 4.0 | deleted 44 characters in body; added 92 characters in body |
| Nov 5, 2021 at 17:42 | comment | added | Jack Creasey | I understand that you need to implement the SRs, but they are built in simple logic gates anyway. Just look at the TTL databook to see an implementation of an SR. You should use at least half to a third of the logic gates using a serial serial implementation. | |
| Nov 5, 2021 at 17:34 | comment | added | Eugene Sh. | Well ,theoretically you can implement memory (flip-flops) using logic gates. How well these will work is a big question. | |
| Nov 5, 2021 at 17:17 | comment | added | Carl Jefferson Lay | @JackCreasey Unfortunately, I am limited to using basic logic gates. | |
| Nov 5, 2021 at 17:17 | comment | added | Carl Jefferson Lay | @jsotola Binary calculator, but the binary output will be transformed into BCD then displayed as decimal numbers on 7 segments. | |
| Nov 5, 2021 at 17:14 | comment | added | Carl Jefferson Lay | @EugeneSh. Ok, I'll try to replace some of the redundant parts with blocks, will update later. | |
| Nov 5, 2021 at 16:42 | history | edited | Carl Jefferson Lay | CC BY-SA 4.0 | added 117 characters in body |
| Nov 5, 2021 at 16:38 | comment | added | Jack Creasey | The major issue you have is approaching it as a parallel problem. You don't need real time results, so use a serial adder. You shouldn't need more than 4 shift registers (two for input numbers and 2 for result) and a small state machine or counter to do the task. This might kick you off: web.njit.edu/~gilhc/ECE394/ECE394-V.htm | |
| Nov 5, 2021 at 16:34 | comment | added | jsotola | is the project requirement a decimal calculator? | |
| Nov 5, 2021 at 15:57 | comment | added | Eugene Sh. | It would be much simpler to analyze if it was drawn as hierarchical design. That is, so the adders are not detailed down to the gate levels and such. | |
| Nov 5, 2021 at 15:56 | comment | added | Stack Exchange Broke The Law | For a school project, is it? Because calculators can be shrunk by reusing the same circuits over and over, but that requires memory elements. | |
| S Nov 5, 2021 at 15:21 | review | First questions | |||
| Nov 5, 2021 at 15:39 | |||||
| S Nov 5, 2021 at 15:21 | history | asked | Carl Jefferson Lay | CC BY-SA 4.0 |