Timeline for Can't provide an input clock signal to an SPI slave implemented in an FPGA through a PMOD pin
Current License: CC BY-SA 4.0
20 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Nov 19, 2021 at 10:13 | history | edited | TonyM | CC BY-SA 4.0 | Correction. Spelling. Removed SHOUTY bold. |
| Nov 19, 2021 at 10:11 | history | edited | Martel | CC BY-SA 4.0 | deleted 56 characters in body |
| Nov 19, 2021 at 9:56 | history | edited | Martel | CC BY-SA 4.0 | deleted 17 characters in body |
| Nov 19, 2021 at 9:56 | vote | accept | Martel | ||
| Nov 18, 2021 at 19:02 | answer | added | Mitu Raj | timeline score: 1 | |
| Nov 18, 2021 at 19:00 | comment | added | TonyM | Why have you put 'it crashes' back, then, when it doesn't? A programme crashing means it goes out of control - this doesn't, though. Your question was clearer and now it's worse. | |
| Nov 18, 2021 at 18:57 | answer | added | Tom Carpenter | timeline score: 3 | |
| Nov 18, 2021 at 18:46 | history | edited | Martel | CC BY-SA 4.0 | added 341 characters in body |
| Nov 18, 2021 at 18:42 | history | edited | TonyM | CC BY-SA 4.0 | Correction. |
| Nov 18, 2021 at 18:41 | comment | added | Martel | It stops with an error. | |
| Nov 18, 2021 at 18:40 | comment | added | TonyM | Does Vivado actually crash or just stop with an error? | |
| Nov 18, 2021 at 18:33 | history | edited | TonyM | CC BY-SA 4.0 | Correctly ordered text. Please do not dump a load of text at the end under 'EDIT' and expect the reader to make sense of two separate explanations. |
| Nov 18, 2021 at 18:26 | history | edited | Martel | CC BY-SA 4.0 | added 949 characters in body |
| Nov 18, 2021 at 17:43 | comment | added | icodeplenty | How have you implemented your slave SPI inside the FPGA? Is it fully custom (your code), or using the Xilinx provided IP? Using the Xilinx IP can have an impact on the signal types, so this is important. | |
| Nov 18, 2021 at 14:58 | history | undeleted | CommunityBot | ||
| Nov 18, 2021 at 14:58 | history | deleted | CommunityBot | via Vote | |
| Nov 18, 2021 at 13:17 | comment | added | Mitu Raj | I wonder if you could screenshot the exact error.... | |
| Nov 17, 2021 at 23:40 | history | edited | TonyM | CC BY-SA 4.0 | Spelling and grammar. Removed shouty bold. |
| Nov 17, 2021 at 22:55 | comment | added | Kartman | What Vivado considers is a clock signal is different to your spi clock. It is simply an input that your logic interprets as the spi clock. | |
| Nov 17, 2021 at 22:47 | history | asked | Martel | CC BY-SA 4.0 |