Timeline for FPGA SPI slave doesn't work if driving it with the fast FPGA clock instead of with the SPI master clock (oversampling)
Current License: CC BY-SA 4.0
6 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Jul 15, 2023 at 20:24 | history | edited | awjlogan | CC BY-SA 4.0 | added 2 characters in body |
| Jul 15, 2023 at 19:57 | history | edited | awjlogan | CC BY-SA 4.0 | added 15 characters in body |
| Nov 22, 2021 at 11:15 | comment | added | awjlogan | I don't think there's any free CDC verification tools. If you have access to paid, then QuestaCDC (Mentor), SpyGlass (Synopsys), and Conformal (Cadence) are the leading tools. If you don't, a simple hack is to set your simulation clocks to non-integer ratios and you might pick up some incorrect transmissions that you wouldn't see with integer ratios. Good resource: sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf | |
| Nov 22, 2021 at 10:51 | comment | added | Martel | Yes, that was the problem, thanks. I use icarus verilog to run my simulations, and I haven't found any flag to make it CDC. What simulators have this capability? | |
| Nov 22, 2021 at 9:43 | vote | accept | Martel | ||
| Nov 21, 2021 at 13:05 | history | answered | awjlogan | CC BY-SA 4.0 |