This is not a math question. What I want to know is physical implementation of the receiver where phase modulated signal is coming to the receiver. How does receiver decides when phase reversal occurs or one bit duration is completed and the second bit is being received. I mean how sender and receiver are synchronized and how the receiver knows when to sample incoming conrinuous signal for processing. In uart protocol, there are start bits and end bits and baud rate is known to receiver so that it can easily know what to do, when to sample bits etc. How the whole thing applies to PSK sitution?

This is not a math question. 

What I want to know is the physical implementation of the receiver where phase modulated signal is coming to the receiver. 

How does the receiver decide when the phase reversal occurs or one bit duration is completed and the second bit is being received? I mean how are the sender and receiver synchronized and how does the receiver know when to sample the incoming continuous signal for processing?

In the UART protocol, there are start bits and end bits and the baud rate is known to the receiver so that it can easily know what to do, when to sample bits etc. 

How does the whole thing apply to the PSK situation?